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| TY00680002/003ADGB TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS TENTATIVE Pseudo SRAM and NOR Flash Memory Mixed Multi-Chip Package DESCRIPTION The TY00680002/003ADGB is a mixed multi-chip package containing a 67,108,864-bit pseudo static RAM and a 268,435,456-bit Nor Flash Memory. The TY00680002/003ADGB is available in a 81-pin BGA package making it suitable for a variety of applications. MCP Features * * * Power supply voltage of 1.70 to 1.95 V Operating temperature of -30 to 85C Package P-TFBGA81-0710-0.80BZ (Weight: 0.15 g) Nor Flash Memory Features * * Organization: 16M x 16 bits Power dissipation Read operation : 40 mA maximum Address Increment Read operation : 8.2 mA maximum Page Read operating : 5 mA maximum Program operation : 20 mA maximum Erase operation : 25 mA maximum Standby : 25 A maximum Access time : Random : 70 ns @CL=30pF Page : 15 ns @CL=30pF Functions Simultaneous Read/Write Page Read Auto Program Auto Page Program(8word) Auto Block Erase Auto Chip Erase Program Suspend/Resume Erase Suspend/Resume Data polling/Toggle bit Password block protection Block protection/ Boot block protection Automatic Sleep, support for hidden ROM area Common Flash memory Interface (CFI) Block erase architecture 8 x 8 Kwords / 255 x 64 Kwords Bank architecture 16 Mbits x 16 Banks Boot block architecture TY00680002ADGB : top boot block TY00680003ADGB : bottom boot block Mode control Compatible with JEDEC standard commands Erase/Program cycles 100,000 cycles typ. Pseudo SRAM Features * * Organization : 4M x 16 bits Power dissipation Operating : 50 mA maximum Standby : 200 A maximum Deep power-down standby : 10 A maximum Access time : Random / Page : 75 ns / 25 ns @CL=30pF Page read operation by 8 words Deep power-down mode : Memory cell data invalid * * * * * * www..com * * * * 2008-10-21 1/9 TY00680002/003ADGB PIN ASSIGNMENT (TOP VIEW) 1 2 3 4 5 6 7 8 A B C D E F G H J K L M NC NC NC A3 A2 A1 A0 CEf CE1ps NC NC A7 A6 A5 A4 VSS OE NC LB UB NC WP NC WE NC A8 A19 A9 A10 DQ6 DQ13 DQ12 DQ5 NC NC A11 A12 A13 A14 NC DQ15 DQ7 DQ14 NC NC RESET RY/ BY f CE2ps A20 A23 NC DQ4 VCCps NC NC A15 A21 A22 A16 NC VSS A18 A17 DQ1 DQ9 DQ10 DQ2 NC NC NC DQ3 VCCf DQ11 NC DQ0 DQ8 NC NC NC NC NC PIN NAMES A0 to A23 DQ0 to DQ15 CE1ps , CE2ps CEf OE WE LB , WP UB RESET RY/ BY f VCCps VCCf www..com VSS NC Address inputs Data inputs / outputs Chip enable inputs for Pseudo SRAM Chip enable inputs for Nor Flash Memory Output enable input Write enable input Data byte control inputs for Pseudo SRAM Write protect for Nor Flash Memory Hardware reset input for Nor Flash Memory Ready/Busy output for Nor Flash Memory Power supply for Pseudo SRAM Power supply for Nor Flash Memory Ground Not connected 2008-10-21 2/9 TY00680002/003ADGB PIN NAME CONVERSION TABLE MCP Pin Location Name A1 NC A2 - A3 - A4 - A5 - A6 - A7 - A8 NC B1 NC B2 NC B3 NC B4 NC B5 NC B6 NC B7 NC B8 NC C1 NC C2 A7 C3 LB C4 WP C5 WE C6 A8 C7 A11 C8 - D1 A3 D2 A6 D3 UB D4 RESET D5 CE2ps D6 A19 D7 A12 D8 A15 E1 A2 E2 A5 E3 A18 E4 RY/ BY f E5 A20 E6 A9 www..com E7 A13 E8 A21 F1 A1 F2 A4 F3 A17 F4 NC F5 A23 F6 A10 F7 A14 F8 A22 64M PSRAM - - - - - - - - - - - - - - - - - A7 LB WE 256M Nor - - - - - - - - - - - - - - - - - A7 - WP WE A8 A11 - A3 A6 UB A8 A11 - A3 A6 - RESET - CE2 A19 A12 A15 A2 A5 A18 - A20 A9 A13 A21 A1 A4 A17 - - A10 A14 - - A19 A12 A15 A2 A5 A18 RY/ BY A20 A9 A13 A21 A1 A4 A17 - A23 A10 A14 A22 MCP Pin Location Name G1 A0 G2 VSS G3 DQ1 G4 NC G5 NC G6 DQ6 G7 NC G8 A16 H1 CEf H2 OE H3 DQ9 H4 DQ3 H5 DQ4 H6 DQ13 H7 DQ15 H8 NC J1 CE1ps J2 DQ0 J3 DQ10 J4 VCCf J5 VCCps J6 DQ12 J7 DQ7 J8 VSS K1 - K2 DQ8 K3 DQ2 K4 DQ11 K5 NC K6 DQ5 K7 DQ14 K8 - L1 NC L2 NC L3 NC L4 NC L5 NC L6 NC L7 NC L8 NC M1 NC M2 - M3 - M4 - M5 - M6 - M7 - M8 NC 64M SRAM A0 GND I/O2 - - I/O7 - A16 - OE 256M Nor A0 VSS DQ1 - - DQ6 - A16 CE OE I/O10 I/O4 I/O5 I/O14 I/O16 - CE1 DQ9 DQ3 DQ4 DQ13 DQ15 - DQ0 DQ10 - DQ12 DQ7 VSS - DQ8 DQ2 DQ11 NC DQ5 DQ14 - - - - - - - - - - - - - - - - - I/O1 I/O11 - VCC VDD I/O13 I/O8 GND - I/O9 I/O3 I/O12 NC I/O6 I/O15 - - - - - - - - - - - - - - - - - 2008-10-21 3/9 TY00680002/003ADGB BLOCK DIAGRAM VCCf A0~A23 VSS A0~A23 WP RESET CEf 256 Mbits FLASH Memory RY/BYf DQ0~DQ15 VCCps A0~A21 VSS WE 64 Mbits PSEUDO SRAM OE CE1ps CE2ps UB LB www..com 2008-10-21 4/9 TY00680002/003ADGB MODE SELECTION Pseudo SRAM MODE Read(Word) Read(Lower Byte) Read(Upper Byte) Write(Word) Write(Lower Byte) Write(Upper Byte) Outputs Disabled Standby Deep Power-down Standby H H H L H X X H X X L H X L L H CE1ps CE2ps OE WE LB L L H L L H X X X UB L H L L H L X X X Add DQ0~DQ7 DOUT DOUT High-Z DIN DQ8~DQ15 DOUT High-Z DOUT DIN Invalid DIN High-Z High-Z High-Z X DIN Invalid High-Z High-Z High-Z Nor Flash Memory MODE Read / Page Read Standby Output Disable Write Hardware Reset / Standby Boot Block Protect CEf OE L X H H X X WE H X H (1) RESET H H X H L X WP DQ0~DQ15 DOUT High-Z High-Z DIN High-Z X L H X L X X X X X X X L X X Notes: L = VIL; H = VIH; X = VIH or VIL Does not apply when (1) Pulse input CEf = VIL and CE1ps = VIL and CE2ps = VIH at the same time. www..com 2008-10-21 5/9 TY00680002/003ADGB ID CODE TABLE TYPE Manufacturer Code TY00680002ADGB Device Code TY00680003ADGB Verify Block Protect Note: * = VIH or VIL , L = VIL H = VIH (1) BA: Block address (2) 0001H: Protected block , 0000H: A23~A12 * * A6 L L A1 L L A0 L H CODE (HEX) 0098H 006Fh 00EFh Data (2) * BA (1) L L L H H L Unprotected block ABSOLUTE MAXIMUM RATINGS SYMBOL VCC VIN VDQ Topr PD Tsolder IOSHORT Tstg PARAMETER VCCps/VCCf Power Supply Voltage Input Voltage Input/Output Voltage Operating Temperature Power Dissipation Soldering Temperature Output Short Circuit Current Storage Temperature (1) RANGE -0.3~2.5 -0.5~2.5 -0.5~VCC + 0.5 ( 3.6) -30~85 UNIT V V V C W C mA C 0.6 260 100 -55~125 Note : (1) Output shorted for no more than one second. No more than one output shorted at a time RECOMMENDED DC OPERATING CONDITIONS (Ta = -30~85C) SYMBOL VCC VIH VIL www..com PARAMETER VCCps/VCCf Power Supply Voltage Input High-Level Voltage Input Low-Level Voltage MIN 1.70 (1) TYP. MAX 1.95 (1) UNIT VCC x 0.8 -0.3 VCC + 0.3 VCC x 0.2 V Note : (1) The potential difference of VCCps and VCCf is less than 0.5 V CAPACITANCE (Ta = 25C, f = 1 MHz) SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance CONDITION VIN = GND VOUT = GND MIN TYP. MAX 17 22 UNIT pF pF Note: These parameters are sampled periodically and are not tested for every device. 2008-10-21 6/9 TY00680002/003ADGB DC CHARACTERISTICS (Ta = -30~85C, VCCps/ VCCf = 1.70 V~1.95 V) SYMBOL IIL IOHps IOLps IOHf IOLf ILO ICCO1f ICCO2f ICCO3f ICCO4f ICCO5f ICCO6f ICCO7f ICCO8f ICCO1ps ICCO2ps ICCSps ICCSDps ICCS1f ICCS2f VLKO PARAMETER Input Leakage Current Pseudo SRAM Output High Current Pseudo SRAM Output Low Current Flash Output High Current Flash Output Low Current Output Leakage Current Flash Random Read Current Flash Program Current Flash Erase Current Flash Read-While-Program Current Flash Read-While- Erase Current Flash Program-while- Erase-Suspend Current Flash Page Read Current Flash Address Increment Read Current(4) Pseudo SRAM Operating Current (2,3) CONDITION VIN = 0 V~VCCf (VCCps) VOH = VCCps - 0.2 V VOL = 0.2 V VOH = VCCf - 0.1 V VOL = 0.1 V VOUT = 0 V~VCCf (VCCps), OE = VIH CEf = VIL, IOUT = 0 mA, tcycle = 100ns CEf = VIL, IOUT = 0 mA CEf = VIL, IOUT = 0 mA MIN -0.5 MAX UNIT 1 1 A mA mA mA mA A 1.0 -0.1 0.1 40 20 25 60 65 20 5 8.2 50 25 200 5 10 10 1.6 mA mA mA mA mA mA mA mA mA mA A A A A VIN = VIH/VIL, IOUT = 0 mA, tcycle = 100 ns VIN = VIH/VIL, IOUT = 0 mA, tcycle = 100 ns VIN = VIH/VIL, IOUT = 0 mA CEf = VIL, IOUT = 0 mA , tRC = 100 ns CEf = VIL, IOUT = 0 mA tRC = 100 ns , tRPC = 25 ns CE1ps = VIL , CE2ps = VIH, IOUT = 0 mA CE1ps = VIL, CE2ps = VIH, Page add. Cycling, IOUT = 0 mA tRC = min tPC = min Pseudo SRAM Page Access Operating Current (2,3) Pseudo SRAM Standby Current (MOS) Pseudo SRAM Deep Power-down Standby Current Flash Standby Current Flash Standby Current (1) (Automatic Sleep Mode ) Low Voltage Lock-out Voltage CE1ps= VCCps - 0.2 V, CE2ps = VCCps - 0.2 V CE2ps = 0.2 V CEf = RESET = VCCf or RESET = VSS VIH = VCCf or VIL = VSS 1.0 V www..com (1) The device is going to Automatic Sleep Mode, when address remain steady during 150 ns. (2) (3) (4) ICCO depends on the cycle time. ICCO depends on output loading. (ICCO1f+ ICCO7f x 7)8word Specified values are defined with the output open condition. See page P-1 to page P-8 for the specification of Pseudo Static RAM. See page F-1 to page F-73 for the specification of Nor Flash Memory. 2008-10-21 7/9 TY00680002/003ADGB PACKAGE DIMENSIONS P-TFBGA81-0710-0.80BZ Unit: mm 0.20 S B 10.00 INDEX 4 0.15 0.10 S S 0.26 0.04 7.00 0.40 0.70 A 0.60 0.20 S A 0.10 S 0.08 INDEX B 0.46 0.05 S AB ABCDEFGHJ KLM 1 2 3 4 5 6 7 8 0.80 0.40 www..com 0.80 1.20 max 2008-10-21 8/9 TY00680002/003ADGB RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 021023_D 070122EBA_R6 * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, www..com etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C * Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 060819_AF * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E 2008-10-21 9/9 TC51YHM616B 64 Mbits PSEUDO STATIC RAM TC51YHM616B Organization : 4M x 16bits www..com 2005-10-20 P-1/8 TC51YHM616B AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = -30C to 85C, VDD = 1.7 to 1.95 V) (See Notes 1 to 5) SYMBOL tRC tACC tCO tOE tBA tCOE tOEE tBE tOD tODO tBD tOH tPM tPRC tAA tAOH tWC tWP tCW tBW tAW tAS tWR tWEHA tCEHA tBEHA tODW PARAMETER Read Cycle Time Address Access Time Chip Enable( CE1 )Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold Time Page Mode Time Page Mode Read Cycle Time Page Mode Address Access Time Page Mode Output Data Hold Time Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Valid to End of Write Address Setup Time Write Recovery Time Write Enable High Pulse Width Chip Enable High Pulse Width Data Byte Control High Pulse Width MIN 75 10 8 0 5 75 25 3 75 50 75 65 65 0 0 6 10 10 MAX 10000 75 75 25 25 15 15 15 10000 25 10000 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns WE Low to Output High-Z WE High to Output Active Data Setup Time Data Hold Time Page Mode Write Bigin Cycle Time Page Mode Write Cycle Time Page Mode Write End Cycle Time Page Mode Write Data Set-up Time Page Mode Write Pulse Width(/WE toggle) Page Mode Write High Pulse Width Page Mode Write Recovery Time CE2 Set-up Time CE2 Hold Time from Deep Power Down CE2 Hold Time from Partial Refresh CE2 Pulse Width CE2 Hold from CE1 CE2 Hold from Power On Address Setup Time from ADV Address Hold Time from ADV ADV Pulse Width 15 ns ns ns ns ns ns ns ns ns ns ns ns us ns ms ns s tOEW tDS tDH www..com tPWC1 tPWC2 tPWC3 tDSP tWPPM tWHP tWRP tCS tCH tCHR tDPD tCHC tCHP tASV tAHV tAVLA tCSV tOEHV tWEHV tMH 0 15 0 75 25 25 15 15 5 10 0 200 5 10 0 50 0 5 12 0 5 5 10 ns ns ns ns ns Ns ns Chip Enable Setup Time from ADV Output Enable Hold Time from ADV Write Enable Hold Time from ADV Mode Register Set Hold Time 2005-10-20 P-2/8 TC51YHM616B AC TEST CONDITIONS PARAMETER Output load Input pulse level Timing measurements Reference level tR, tF CONDITION As shown in Fig.1 VDD - 0.2 V, 0.2 V VDD x 0.5 VDD x 0.5 2 ns Fig.1 I/O Z0 = 50ohm 50ohm CL = 30pF VDD x 0.5 www..com 2005-10-20 P-3/8 TC51YHM616B TIMING DIAGRAMS READ CYCLE tRC Address A0 to A21 tACC tCO tOH CE1 CE2 tOE OE tODO WE Fix-H tOD tBA UB , LB tBE DOUT I/O1 to I/O16 tBD VALID DATA OUT Hi-Z tOEE Hi-Z tCOE INDETERMINATE PAGE READ CYCLE (8 words access) tPM tRC Address A0 to A2 www..com Address tPRC tPRC tPRC A3 to A21 CE1 CE2 OE Fix-H WE UB , LB tBA DOUT I/O1 to I/O16 tOEE tBE Hi-Z tCOE tCO tACC DOUT tAA tOE tAOH DOUT tAA tAOH tAOH DOUT tAA tBD tOH DOUT tODO Hi-Z tOD * Maximum 8 words 2005-10-20 P-4/8 TC51YHM616B WRITE CYCLE 1 ( WE CONTROLLED) (See Note 4) tWC Address A0 to A21 tAS WE tAW tWP tWR tWEHA tCW CE1 tWR CE2 Fix-H tBW tWR UB , LB tBE DOUT I/O1 to I/O16 DIN I/O1 to I/O16 Hi-Z tCOE (See Note 5) tDS tDH (See Note 5) tODW Hi-Z VALID DATA IN WRITE CYCLE 2 ( CE CONTROLLED) (See Note 4) tWC Address A0 to A21 www..com tAW tAS tWP tWR WE tCEHA tCW CE1 tWR CE2 Fix-H tBW tWR UB , LB tBE DOUT I/O1 to I/O16 DIN I/O1 to I/O16 Hi-Z tCOE tDS tDH tODW Hi-Z (See Note 5) VALID DATA IN 2005-10-20 P-5/8 TC51YHM616B WRITE CYCLE 3 ( UB, LB CONTROLLED) (See Note 4) tWC Address A0 to A21 tAW tAS WE tWP tWR tCW CE1 tWR CE2 Fix-H tBW tWR tBEHA UB , LB tCOE DOUT I/O1 to I/O16 Hi-Z tBE tDS DIN I/O1 to I/O16 (See Note 5) tDH tODW Hi-Z VALID DATA IN PAGE WRITE CYCLE (8 words access ) tPM tPWC1 Address A0 to A2 www..com Address tPWC2 tPWC2 tPWC3 tWR tAS tWR tAS tWR tAS A3 to A21 tWRP CE1 CE2 Fix-H tWHP tWPPM tWHP tWPPM tWHP tWPPM WE UB , LB tBW tWP tDSP DIN I/O1 to I/O16 (See Note 5) tCW tAW DIN tDH tDSP tDH DIN tDSP tDH DIN tDSP tDH DIN 2005-10-20 P-6/8 TC51YHM616B Deep Power-down Timing CE1 tDPD CE2 tCS tCH Partial Refresh Timing CE1 CE2 tCS tCHR Power-on Timing VDD VDD min CE1 tCHC CE2 tCHP tCH www..com 2005-10-20 P-7/8 TC51YHM616B Provisions for Address Skew Read If multiple invalid address cycles shorter than tRCmin are sustained over 10s in an active state, as least one valid address cycle(with address change of any pins of A3-A21) over tRCmin is needed during the 10s. over 10s CE1 WE Address tRCmin Write If multiple invalid address cycles shorter than tWCmin are sustained over 10s in an active state, as least one valid address cycle(with address change of any pins of A3-A21) over tWCmin with tWPmin is needed during the 10s. over 10s CE1 tWPmin WE Address tWCmin Notes: (1) AC measurements are assumed tR, tF = 2 ns. condition and are not output voltage reference levels. (2) Parameters tOD, tODO, tBD, tODW, tKQX, tCEHZ and tOEHZ define the time at which the output goes into the open www..com (3) (4) (5) Data cannot be retained during deep power-down stand-by mode. If OE is high during the write cycle, the outputs will remain at high impedance. During the output state of I/O signals, input signals of reverse polarity must not be applied. 2005-10-20 P-8/8 256Mbits NOR FLASH MEMORY PAGE 256 Mbits NOR FLASH MEMORY TC58FYM8T7D : Top Boot Block TC58FYM8B7D : Bottom Boot Block Organization : 16M x 16bits www..com 2008-03-19 F-1/73 256Mbits NOR FLASH MEMORY PAGE 1. MODE SELECTION Mode Read Cycle Command Write L Cycle H Standby X Output Disable Hardware Reset/Standby Boot Block Protect (2) CE L OE L H X X H X X WE WP A23-A0 Addr In Addr In X X X X X RESET H H H L X L X DQ0~DQ15 DOUT DIN High-Z High-Z High-Z High-Z X H (1) X X X X X X X X X X X L X X X Notes: X: VIH or VIL L: VIL H: VIH (1) Pulse Input (2) When WP =VIL, BA0-BA1 in Bottom Boot block device and BA261-BA262 in Top Boot Block device are protected. 2. ID CODE TABLE CODE TYPE Manufacturer Code Top Boot Block Device Code Bottom Boot Block Verify Block Protect X BA (1) A23~A13 X X A6 L L L L A1 L L L H A0 L H H L CODE (HEX) 0098h 006Fh 00EFh Data (2) X: VIH or VIL L: V H: V IH www..com IL (1) BA: Block Address (2) 0001h-Protected Block , 0000h- Unprotected Block Notes : 2008-03-19 F-2/73 256Mbits NOR FLASH MEMORY PAGE 3. COMMAND SEQUENCES BUS COMMAND SEQUENCE WRITE CYCLES REQ'D Read/Reset Read/Reset ID Read Auto Program Auto Page Program (8word) Program Suspend Program Resume Auto Chip Erase Auto Block Erase Block Erase Suspend Block Erase Resume Hidden ROM Mode Entry Hidden ROM Program Hidden ROM Erase Hidden ROM Protect Hidden ROM Exit CFI 11 1 1 6 6 1 1 3 4 6 4 4 2 BK 555h BK BK (3) (3) FIRST BUS WRITE CYCLE Addr. XXXh 555h 555h 555h Data F0h AAh AAh AAh AAh B0h 30h AAh AAh B0h 30h AAh AAh AAh AAh AAh 98h SECOND BUS WRITE CYCLE Addr. Data THIRD BUS WRITE CYCLE Addr. Data FOURTH BUS WRITE CYCLE Addr. Data FIFTH BUS WRITE CYCLE Addr. Data SIXTH BUS WRITE CYCLE Addr. Data 1 3 3 4 2AAh 2AAh 2AAh 2AAh 55h 55h 55h 55h 555h BK (3) F0h 90h A0h E6h RA IA (1) RD ID (2) + (4) (6) (6) (5) (7) (7) (6) (7) (6) (7) 555h 555h 555h PA PA PD PD PA PD PA PD 555h 555h BK (3) (3) 2AAh 2AAh 55h 55h 555h 555h 80h 80h 555h 555h AAh AAh 2AAh 2AAh 55h 55h 555h BA (9) 10h 30h BK 555h 555h 555h 555h 555h (3) 2AAh 2AAh 2AAh 2AAh 2AAh CA (9) 55h 55h 55h 55h 55h CD (10) 555h 555h 555h 555h 555h 88h A0h 80h 60h 90h PA (6) PD (7) 555h X1Ah XXXh AAh 68h 00h 2AAh 55h BA (8) 30h + 55h www..com 2008-03-19 F-3/73 256Mbits NOR FLASH MEMORY PAGE 3. COMMAND SEQUENCES (continue) BUS COMMAND SEQUENCE CYCLES REQ'D Addr. 555h Password Program 4 555h 555h Password Unlock Password Verify Password Protection Mode Lock Set Non-Password Protection Mode Lock PPB Set PPB Clear Verify Block Protect PPB Lock Set PPB Lock Verify DPB Set DPB Clear DPB Verify 4 3 4 4 4 4 555h 555h 555h 555h 555h 555h AAh AAh AAh AAh AAh AAh 2AAh 2AAh 2AAh 2AAh 2AAh 2AAh 55h 55h 55h 55h 55h 55h BA 6 6 555h 555h AAh AAh 2AAh 2AAh 55h 55h 555h 555h (8) FIRST BUS SECOND BUS THIRD BUS WRITE CYCLE Addr. 555h 555h 555h 555h 555h 555h Data 38h 38h 38h 38h 28h C8h FOURTH BUS WRITE CYCLE Addr. XX0h XX1h XX2h XX3h XX0h PWA (12) FIFTH BUS SIXTH BUS SEVENTH BUS WRITE WRITE CYCLE WRITE CYCLE Data AAh AAh AAh AAh AAh AAh Addr. 2AAh 2AAh 2AAh 2AAh 2AAh 2AAh Data 55h 55h 55h 55h 55h 55h WRITE CYCLE WRITE CYCLE WRITE CYCLE Addr. Data Addr. Data Addr. Data Data PD0 PD1 PD2 (11) (11) (11) (11) (11) (13) 555h PD3 PD0 7 4 555h 555h XX1h PD1 (11) XX2h PD2 (11) XX3h PD3 (11) PWD 6 555h AAh 2AAh 55h 555h 60h X0Ah 68h 6 555h AAh 2AAh 55h 555h 60h X12h (8) 68h 60h 60h 90h 78h 58h 48h 48h 58h BA +X02h 68h 60h (14) X02h BA (8) + 555h +X02h PD(0) 555h 555h 555h 555h 555h BA (8) (8) (8) (8) PD(1) (14) BA BA BA X1h X0h PD(0) (14) Notes: The system should generate the following address patterns: 555h or 2AAh on address pins A10~A0. DQ8~DQ15 are ignored. X : VIH or VIL (0h-Fh) www..com (1) (2) (3) (4) RA: Read Address RD: Read Data Output BK: Bank Address = A23~A20 IA: Bank Address and ID Read Address(A6,A1,A0) Bank Address = A23~A20 Manufacturer Code = (0,0,0) Device Code = (0,0,1) (5) ID: ID Code Output (6) PA: Program Address Input continuous 8 addresses from (A0,A1,A2) = (0, 0, 0) to (1,1,1) in Page program. (7) PD: Program Data Input Input continuous 8 address from (A0,A1,A2) = (0,0,0) to (1,1,1) in Page program. BA: Block Address = A23~A13 CA: CFI Address CD: CFI Data Output PD0 : 1st Password (Data of 1-16bit) PD1 : 2nd Password (Data of 17-32bit) PD2 : 3rd Password (Data of 33-48bit) PD3 : 4th Password (Data of 49-64bit) PWA: Password Address Input PWD: Password Data Output PD(0): Data (1: Set/ 0: Clear) on DQ0. PD(1): Data (1: Set/ 0: Clear) on DQ1. (8) (9) (10) (11) (12) (13) (14) 2008-03-19 F-4/73 256Mbits NOR FLASH MEMORY PAGE 4. SIMULTANEOUS READ/WRITE OPERATION The TC58FYM8T7D/B7D features a Simultaneous Read/Write operation. The Simultaneous Read/Write operation enables the device to simultaneously write data to or erase data from a bank while reading data from another bank. The TC58FYM8T7D/B7D has a total of 16 Banks (16Mbits x 16 Banks). Banks can be switched by using the bank addresses (A23~A20). For a description of bank blocks and addresses, please refer to the Block Address Table and Block Size Table. The Simultaneous Read/Write operation cannot perform multiple operations within a single bank. The table below shows the operation modes in which simultaneous operation can be performed. Note that during Auto-Program execution or Auto Block Erase operation, the Simultaneous Read/Write operation cannot read data from addresses in the same bank which have not been selected for operation. However, Data from these addresses can be read using the Program Suspend or Erase Suspend function. In order to perform simultaneous operation during automatic operation execution, when changing a bank, it is necessary to set OE to VIH. SIMULTANEOUS READ/WRITE OPERATION STATUS OF BANK ON WHICH OPERATION IS BEING PERFORMED Read Mode ID Read Mode Auto-Program Mode Auto-Page Program Mode Program Suspend Mode Auto Block Erase Mode Erase Suspend Mode Program during Erase Suspend Program Suspend during Erase Suspend CFI Mode Password Unlock Notes: www..com Excluding times when Acceleration Mode is in use. Read Mode STATUS OF OTHER BANKS 2008-03-19 F-5/73 256Mbits NOR FLASH MEMORY PAGE 5. OPERATION MODES In addition to the Read, Write and Erase Modes, the TC58FYM8T7D/B7D features many functions including block protection and data polling. When incorporating the device into a design, please refer to the timing charts and flowcharts in combination with the descriptions below. 5.1. Read Mode To read data from the memory cell array, set the device to Read Mode. The device is automatically set to Read Mode immediately after power-on or on completion of an automatic operation. The Software Reset Command releases the ID Read Mode, releases the lock state when an automatic operation ends abnormally, and sets the device to Read Mode. Hardware Reset terminates operation of the device and resets it to Read Mode. When reading data without changing the address immediately after power-on, the host should input Hardware Reset or change CE from High to Low. This mode can execute high-speed random access and Page Read (8 words). The appropriate page area is selected by address pins A0-A2. When reading data from a memory cell array, the address (A23-A0) must be input under CE = VIL, WE = VIH . After the address is acknowledged, the data is outputted to DQ0-DQ15. And 1'st read just after command input need tWEHH + tACC. 5.2. ID Read ID Read Mode is used to read the Manufacture code and the Device code. The mode is useful in that it allows EPROM programmers to identify the device type automatically. Access time in ID Read Mode is the same as that in Read Mode. However 1st access after command input need tWEHH + tACC. For a list of the codes, please refer to the ID Code Table. Inputting an ID Read command sets the specified bank to ID Read Mode. Banks are specified by inputting the bank address (BK) in the third Bus Write cycle of the Command cycle. To read an ID code, the bank address as well as the ID read address must be specified. The Manufacture code is output from address BK + 00; the device code is output from address BK + 01. From other banks, data is output from the memory cells. Inputting a Reset command releases ID Read Mode and returns the device to Read Mode. 5.3. Standby Mode TC58FYM8T7D/B7D has two ways to put the device into Standby Mode. In Standby Mode, DQ is put into the High-Impedance state. (1) Control using CE and RESET With the device in Read Mode, input VIH to CE and RESET . The device will enter Standby Mode. www..com However, if the device is in the process of performing simultaneous operation, the device will not enter Standby Mode but will instead cause the operating current to flow. (2) Control using RESET only With the device in Read Mode, input VIL to RESET . The device will enter Standby Mode. Even if the device is in the process of performing simultaneous operation, this method will terminate the current operation and set the device to Standby Mode. This is a hardware reset and is described later. 5.4. Auto-Sleep Mode This function suppresses power dissipation during reading. If the address input does not change for 150 ns, the device will automatically enter Sleep Mode and the current will be reduced to the standby current (IDDS2). However, if the device is in the process of performing simultaneous operation, the device will not enter Standby Mode but will instead cause the operating current to flow. Because the output data is latched, data is output in Sleep Mode. When the address is changed, Sleep Mode is automatically released, and data from the new address is output. 5.5. Output Disable Mode Inputting VIH to OE disables output from the device and sets DQ to High-Impedance. 2008-03-19 F-6/73 256Mbits NOR FLASH MEMORY PAGE 5.6. Ready pin (Ready/Busy pin) The RY/ BY pin indicates the status of auto operation as the Ready/Busy pin. During an auto operation, the RY/ BY pin outputs VOL. At the end of auto operation, the RY/ BY pin outputs Hi-Z. The RY/ BY pin behaves as an open-drain type circuit. 5.7. Command Write The TC58FYM8T7D/B7D uses the standard JEDEC control commands for a single-power supply E2PROM. A Command of Write is executed by inputting the address and data into the Command Register. The command is written by inputting a pulse to WE with CE = VIL and OE = VIH ( WE control). The command can also be written by inputting a pulse to CE with WE = VIL ( CE control). The address is latched on the falling edge of either WE or CE . DQ0~DQ7 are valid for data input and DQ8~DQ15 are ignored. To abort input of the command sequence uses the Reset command. The device will reset the Command Register and enter Read Mode. If an undefined command is input, the Command Register will be reset and the device will enter Read Mode. 5.8. Software Reset: Read/Reset Command Initiate the software reset by inputting a Read/Reset command. The software reset returns the device from ID Read Mode or CFI Mode to Read Mode, releases the lock state if automatic operation has ended abnormally, and clears the Command Register. 5.9. Hardware Reset The Hardware Reset initializes the device and sets it to the Read Mode. When a pulse is input to RESET for tRP, the device abandons the operation which is in progress and enters the Read Mode after tREADY. Note that if a Hardware Reset is applied during data overwriting, such as a Write or Erase operation, data at the address or block being written to at the time of the reset will become undefined. After a Hardware Reset, the device enters Read Mode if RESET = VIH or Standby Mode if RESET = VIL. The DQ pins are High-Impedance when RESET = VIL. After the device has entered Read Mode, Read operations and input of any command are allowed. 5.10. Comparison between Software Reset and Hardware Reset ACTION Releases ID Read Mode or CFI Mode SOFTWARE RESET True True True False False HARDWARE RESET True True True True True www..com Clears the Command Register Releases the lock state if automatic operation has ended abnormally Stops any automatic operation which is in progress Stops any operation other than the above and returns the device to Read Mode 2008-03-19 F-7/73 256Mbits NOR FLASH MEMORY PAGE 5.11. Auto-Program Mode The TC58FYM8T7D/B7D can be programmed in word units. Auto-Program Mode is set using the Program command. The program address and program data is latched in the fourth Bus Write cycle. Auto programming starts on the rising edge of the WE signal in the fourth Bus Write cycle. The Program and Program Verify commands are automatically executed by the chip. The device status during programming is indicated by the Hardware Sequence flag. To read the Hardware Sequence flag, specify the address to which the Write is being performed. During Auto Program execution, a command sequence for the bank on which execution is being performed cannot be accepted. To terminate execution, use a Hardware Reset. Note that if the Auto-Program operation is terminated in this manner, the data written so far is invalid. Any attempt to program a protected block is ignored. In this case, the device enters Read Mode 5 s (typ.) after a latch of program data in the fourth Bus Write cycle. If an Auto-Program operation fails, the device remains in the programming state and does not automatically return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a Hardware Reset is required to return the device to Read Mode after a failure. If a programming operation fails, the device should not be used. To build a more reliable system, the host processor should take measures to prevent subsequent use of failed blocks. The device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into cells which contain 0s. If this is attempted, execution of Auto Program will fail. This is a user error, not a device error. A cell containing 0 must be erased in order to set it to 1. 5.12. Auto-Page Program Mode Auto-Page Program is a function which enables simultaneously Programming 8words of data. In this mode, the Programming time for 256M bits is about 50% compared with the Auto program mode. In word mode, input the page program command during first bus write cycle to third bus writes cycle. Input program data and address of (A0,A1,A2) = (0,0,0) in the forth bus write cycle. Input increment address and program data during the fifth bus write cycle to the 11th bus write cycle. After input of the 11th bus write cycle, page program operation starts. Word size and address group in Page program Third bus writes cycles command E6h Word size Address Group 8word program 0007h 080Fh 1017h 181Fh 2027h ---------- www..com 2008-03-19 F-8/73 256Mbits NOR FLASH MEMORY PAGE 5.13. Program Suspend/Resume Mode Program Suspend is used to enable a Data Read by suspending the Write operation. The device accepts a Program Suspend command in Write Mode (including Write operations performed during Erase Suspend) but ignores the command in other modes. When the command is input, the address of the bank on which Write is being performed must be specified. In Program Suspend Mode, it is invalid except a Read/Reset command, an ID Read command, a CFI Read command, and a Resume command. After input of the command, the device will enter Program Suspend Read Mode after tSUSP. When Data Write is suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read are the same as usual. After completion of Program Suspend, input a Program Resume command to return to Write Mode. When inputting the command, specify the address of the bank on which Write is being performed. If the ID Read or CFI Data Read function is being used, abort the function before inputting the Resume command. On receiving the Resume command, the device returns to Write Mode and resumes outputting the Hardware Sequence flag for the bank to which data is being written. 5.14. Auto Chip Erase Mode The Auto Chip Erase Mode is set using the Chip Erase command. An Auto Chip Erase operation starts on the latch of the command in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the Hardware Sequence flag. Command input is ignored during an Auto Chip Erase. A Hardware Reset can interrupt an Auto Chip Erase operation. If an Auto Chip Erase operation is interrupted, it cannot be completed correctly. Hence, an additional Erase operation must be performed. Any attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not be executed and the device will enter Read mode about 1ms after the latch of command in the sixth bus cycle. If an Auto Chip Erase operation fails, the device will remain in the erasing state and will not return to the Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware reset is required to return the device to Read Mode after a failure. In this case, it cannot be ascertained which block the failure occurred in. Either abandon use of the device altogether, or perform a Block Erase on each block, identify the failed blocks, and stop using them. To build a more reliable system, the host processor should take measures to prevent subsequent use of failed blocks. 5.15. Auto Block Erase The Auto Block Erase Mode is set using the Block Erase command. The block address is latched in the sixth bus cycle. Once operation starts, all memory cells in the selected block are automatically preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the setting of the Hardware Sequence flag. When the Hardware Sequence flag is read, the addresses of the blocks on which auto-erase www..com operation is being performed must be specified. All commands (except Erase Suspend) are ignored during an Auto Block Erase operation. Either operation can be aborted using a Hardware Reset. If an Auto Erase operation is interrupted, it cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing. Any attempt to erase a protected block is ignored. If the selected block is protected, the Auto Erase operation is not executed and the device returns to Read Mode 20s (typ.) after the latch of command in the last bus cycle. If an Auto Block Erase operation fails, the device remains in the Erasing state and does not return to Read Mode. The device status is indicated by the Hardware Sequence flag. After a failure, either a Reset command or a Hardware Reset is required to return the device to Read Mode. If an Auto Block Erase operation fails, the device should not be used. To build a more reliable system, the host processor should take measures to prevent subsequent use of failed blocks. 2008-03-19 F-9/73 256Mbits NOR FLASH MEMORY PAGE 5.16. Erase Suspend/Erase Resume Modes Erase Suspend Mode suspends Auto Block Erase and reads data from or writes data to an unselected block. The Erase Suspend command is allowed during an Auto Block Erase operation but it is ignored in all other operation modes. When the command is input, the address of the bank on which Erase is being performed must be specified. In Erase Suspend Mode, it is invalid except a Read/Reset command, an ID Read command, a CFI Read command, a Program command, and a Resume command. If an Erase Suspend command is input during an Auto Block Erase, the device will enter Erase Suspend Read Mode after tSUSE. The device status (Erase Suspend Read Mode) can be verified by checking the Hardware Sequence flag. If data is read consecutively from the block selected for Auto Block Erase, the DQ2 output will toggle and the DQ6 output will stop toggling and RY/ BY will be set to High-Impedance. Inputting a Write command during an Erase Suspend enables a Write to be performed to a block which has not been selected for the Auto Block Erase. Data is written in the usual manner. To resume the Auto Block Erase, input an Erase Resume command. On input of the command, the address of the bank on which the Write was being performed must be specified. On receiving an Erase Resume command, the device returns to the state it was in when the Erase Suspend command was input. If an Erase Resume command is input during an Auto Block Erase, Erase resumes. At this time toggle output of DQ6 resumes and 0 is output on RY/ BY . www..com 2008-03-19 F-10/73 256Mbits NOR FLASH MEMORY PAGE 5.17. Block Protection TC58FYM8T7D/B7D has Block Protection that is a function for disabling writing and erasing specific blocks. Block Protection features several level of Block Protection. (1) Write Protect ( WP pin) [Hardware Protection] The TC58FYM8T7D/B7D has Hardware Block protection feature by WP =VIL. The TC58FYM8T7D protects BA261 and BA262 with WP =VIL. TC58FYM8B7D protects BA0 and BA1 with WP =VIL. This mode is released with WP =VIH. When the device is programming operation or erasing operation, WP pin has to fix to VIH or VIL. (2) Block Protection 1 Persistent Protection Bit(PPB) [Software Protection] By using Persistent Protection Bit, protection can be set to each block. The PPBs retains the state across power cycle. Each PPB can be individually set through the PPB Set command. All PPB can be cleared by the PPB Clear Command at a time. The PPB Verify command to the device can check the PPB status. The PPB set and the PPB clear are an auto operation same as the auto erase and auto program. An auto operation starts from the command latch in the 4th write bus cycle of the PPB Set and the PPB clear. The status of the PPB set and the PPB clear are indicated by the below hardware sequence flags. When completely finish the PPB set and the PPB clear, whether the block is protect or unprotect is indicated by the verify block protect command. Therefore, whether the PPB is set or clear is indicated by verify protect command, when the device is unprotected by other protect like ABP , WP , RESET ,DPB. When the device outputs `1' on DQ0 at the fourth bus write cycle of the PPB verify command, the PPB is Set. When the device outputs `0' on DQ0, the PPB is clear. If an auto operation fails, either a Hidden ROM exit command or a Hardware Reset is required to return the device to Read Mode. When PPB is locked by the PPB Lock Set command, PPB is disabled for PPB Set and PPB Clear Operation. The PPB Lock Verify command can check the PPB Lock status on the DQ1 (`1' is Locked state and `0' is Unlocked state). Behaviors of PPB Lock differ between password protection mode and non-password protection mode. At the time of the finishing PPB Set, PPB Clear, PPB Lock Set and PPB Lock Verify, the hosts have to input the Hidden ROM Exit command. At the time of shipment, the PPBs and PPB Lock are settled to "0". (3) Block Protection 2 Dynamic Protection Bit (DPB) [Software Protection] By using Dynamic Protection Bit, protection can be set to each block. After power-up or hardware reset cycle, all DPB are settled to "0" as clear. Each DPB can be individually modifiable through the DPB Set command and DPP Clear command. The Writing of the DPB Verify command to the device can check the Set or Clear of the DPB status. When completely finish the DPB Set, the device will be outputting `1' on DQ0 at the fourth bus write cycle in the DPB verify command. When the device is outputting `0' on www..com DQ0, the DPB Set is not complete, then the hosts must retry from the DPB set command. Similarly, when completely finish the DPB Clear, the device will be outputting `0' on DQ0 at the fourth bus write cycle in the DPB verify command. When the device is outputting `1' on DQ0, the DPB Clear is not complete, then the user must retry from the DPB clear command. At the time of the finishing DPB Set, DPB Clear, and DPB Verify, the hosts have to input the Hidden ROM Exit command. The hardware Sequence Flags of the PPB set DQ7 In progress Set finished Set Failed 0 1 0 DQ6 Toggle 1 Toggle DQ5 0 0 1 DQ4 0 0 0 DQ3 0 0 0 DQ2 1 1 1 DQ1 0 0 0 DQ0 0 0 0 RY/ BY 0 High-Z 0 The hardware Sequence Flags of the PPB clear DQ7 In progress Clear finished Clear Failed 0 1 0 DQ6 Toggle 1 Toggle DQ5 0 0 1 DQ4 0 0 0 DQ3 1 1 1 DQ2 Toggle 1 N/A DQ1 0 0 0 DQ0 0 0 0 RY/ BY 0 High-Z 0 2008-03-19 F-11/73 256Mbits NOR FLASH MEMORY PAGE 5.17.1 Relationship of the Each Block Protection Block Protection 1 (PPB) (Non-Password Protection mode) Block Protection 1 (PPB) (Password Protection mode) Block Protection 2 (DPB) Power-Up Power-Up Power-Up PPB Lock is an Unlocked state (PPB Set/Clear is enabled) PPB Lock is a Locked state (PPB Set/Clear is disabled) DPB is a cleared state Power-up cycle or Hardware Reset Password Unlock Command PPB Lock is an Unlocked state PPB Lock is a Locked state (PPB Set/Clear is disabled) (PPB Set/Clear is enabled) Power-up cycle or PPB Lock Set or Hardware Reset PPB Lock Set Command PPB Set PPB Clear Device Protect State DPB Set DPB Clear * Either PPB set or DPB set protects an object block. 5.17.2. Block Protection Matrix Hardware Protection Software Protection PPB Clear DPB Bottom Boot : Block 0,1 Clear X Set Clear X Protect X Set Protect Unprotect Unprotect Protect Protect X Clear H Set Unprotect Block Protect Status Top Boot : Block 261,262 Other Block WP RESET www..com H Set Notes X: H or L, Set state or Clear state 2008-03-19 F-12/73 256Mbits NOR FLASH MEMORY PAGE 5.17.3. Non-Password Protection Mode and Password Protection Mode At Block Protection 1, there are two Protection Mode of Non-Password Protection Mode and Password Protection Mode. Operation of a PPB lock differs in each mode. The hosts need to choose either Non-Password Protection Mode or Password Protection Mode before using of this device. Non-Password Protection Mode Lock Command sets the device to Non-Password Protection Mode. Password Protection Mode Lock Command sets the device to Password Protection Mode. Hosts can execute either of Password Lock or Non-Password Lock only once, and Mode Lock Erase is impossible. At the shipment, the Non-Password Protection Mode and the Password Protection Mode aren't set state. In the case of using Non-Password Protection Mode, the hosts have to execute a Non-Password Protection Mode Lock in order to prevent the device from being changed to Password Protection Mode. In the case of using Password Protection Mode, the hosts have to execute a Password Protection Mode Lock. Once a Protection Mode is set, it is not eternally changeable. When the Protection Mode Lock (Set) is finished, the hosts have to execute the Hidden ROM Exit command. The Password Protection Mode Lock and the Non-Password Protection Mode Lock time is tPPRW (Auto PPB set time). Non-Password Protection Mode Lock 0 Set ("1") 0 Set ("1") Password Protection Mode Lock 0 0 Set ("1") Set ("1") Device Status Non-Password Protection Mode (At Shipment) Non-Password Protection Mode Password Protection Mode Inhibit The hardware sequence flags of non-password protect mode lock and password protect mode lock DQ7 In progress Protect finished Protect failed 0 1 0 DQ6 Toggle 1 Toggle DQ5 0 0 1 DQ4 0 0 0 DQ3 0 0 0 DQ2 1 1 1 DQ1 0 0 0 DQ0 0 0 0 RY/ BY 0 High-Z 0 5.17.4. PPB Lock in Non-Password Protection Mode and Password Protection Mode In the case of Non-Password Protection Mode, the PPB Lock is cleared by power-up cycle and Hardware Reset. When PPB Lock is set, the PPBs are disabled for modification by Block Protection 1. After Power-up cycle or www..com Reset again, PPB Lock becomes `0' as clear. In Non-Password Protection Mode, Password Unlock Hardware command is ignored. In the case of Password Protection Mode, the PPB Lock is set by power-up cycle and Hardware Reset. Once Password Protection Mode is set, PPB is disabled for modification by PPB Set and Clear without the Password Unlock command. The state of PPB Lock doesn't differ before and after Password Protection Mode Lock Command. PPB Lock is set again by power-up cycle, Hardware Reset, or PPB lock Set. After entering Password Protection Mode, Password Program command and Password Verify command is permanently ignored. Therefore, when the user chooses the Password Protection Mode, it is necessary to program a 64-bit password to this device before performing a password protection mode lock command. After Password program command, the user has to check by Password Verify command whether the desired Password is correctly programmed. Once Password Protection Mode was set, the user cannot check the Password. At modifying PPB, the user has to use the Password Unlock command with a 64-bit password. Please set a Password certainly. PPB Lock Status of the Non-Password Protection Mode and the Password Protection Mode Non-Password Protection Mode After Power-up cycle or Hardware Reset PPB Lock is `0' (clear) Password Protection Mode PPB Lock is `1' (set) 2008-03-19 F-13/73 256Mbits NOR FLASH MEMORY PAGE PPB Lock Status change method of the each Protection Mode Non-Password Protection Mode Password Protection Mode PPB Set Command PPB Lock Set PPB Lock Set Power-up cycle Hardware Reset Power-up cycle PPB Lock Clear Password Unlock Command Hardware Reset 5.17.5. Description of Password Protection Command (1) Password Program Command The Password Protect Command permits programming the password that is used as part of the Hardware Protection scheme. The actual Password length is 64-bits. The 64-bits password is split to four of 16-bits Password Program. In Password Protection Mode, Password Program and Password verify are disabled. During programming the Password, Simultaneous Operation is disabled. Read operations to any memory location is available after completion of the password programming. The status of password program operation can be checked by hardware sequence flags. When this mode is finished, the hosts have to execute the Hidden ROM Exit command. Password is set as four words of "FFFFh" at the time of shipment. Password programming time is equal to tPPW (Auto Word Program time). The Hardware Sequence Flags of the Password Program DQ7 In Progress Program Complete Program Failed 0 1 0 DQ6 Toggle 1 Toggle DQ5 0 0 1 DQ4 0 0 0 DQ3 0 0 0 DQ2 1 1 1 DQ1 0 0 0 DQ0 0 0 0 RY/ BY 0 High-Z 0 (2) Password Verify Command The Password Verify Command is verify the Password. Verification of a Password can be performed when the Password Protection Mode Lock is not programmed. In Password Protection Mode, if the user attempts to verify the Password, the device output "FFFFh". During verification the Password, Simultaneous Operation is disabled. At the forth bus write cycle of Password Verify Command, the hosts have to fix the two address bits (A1, A0). When this mode is finished, the hosts have to execute the Hidden ROM Exit command. www..com (3) Password Unlock Command The Password Unlock Command clears the PPB Lock Bit when the user sets the Password Protection Mode. In order to perform Password Unlock command, the exact Password is necessary. It is necessary to input password unlock command at intervals of 11s or more. If the interval is shorter than 11s, the command is ignored. At Password Unlock Command the 64-bits password is input in four step at 4th, 5th, 6th, 7th write bus cycles. The address A1:A0 is 0:0 at 4th write bus cycle, A1:A0 is 0:1 at 5th write bus cycle, A1:A0 is 1:0 at 6th write bus cycle, and finally A1:A0 is 1:1 at 7th write bus cycle. A wrong Password input at the Password Unlock sequence causes mismatch of Password and PPB Lock Bit is not changed. When the Password Unlock Command is entered, the RY/ BY pin is Low, which is indicating the device is busy. The status of password unlock operation can be checked by hardware sequence flags. Then flags are output by specifying the address of Bank0 (Bottom Boot Block) or Bank15 (Top Boot Block). Inputting address of the other Bank then, actual cell array data is output. The hardware sequence flags indicate whether exact password is inputted at 4-6th write bus cycles by intervals of 11s or more. During inputting password at 4-7th write bus cycles, DQ6 is toggling. When the first Password Unlock is successful, RY/ BY pin is LOW and DQ6 stop toggling. Then user can input next password. When the Password Unlock Command operation completes, the user has to perform Hidden ROM Exit command. PPB Lock Bit should be read in order to check whether Password Unlock has completed successfully. 2008-03-19 F-14/73 256Mbits NOR FLASH MEMORY PAGE Status Flags of progressing the Password Unlock Command DQ7 PWD Unlock in Progress Finished Input PWD Finished Input PWD Finished Input PWD (1) (1) (4) DQ6 Toggle 1 1 DQ5 0 0 0 DQ4 0 0 0 DQ3 0 0 0 DQ2 1 1 1 DQ1 0 0 0 DQ0 0 0 0 RY/ BY 0 0 High-Z High-Z 0 0 1 (2) (3) Array Data Notes: (1) Specified BA within Bank-0 (Bottom Boot Block Device)/ Bank-15 (Top Boot Block Device) (2) After inputting PWD at the 4th ,5th and 6th bus write cycles, DQ7 is "0" (3) After inputting PWD at the 7th bus write cycle, DQ7 is "1" (4) Specified BA without Bank-0 (Bottom Boot Block Device)/ Bank-15 (Top Boot Block Device) 5.17.6. Verify Block Protect The Verify Block Protect command is used to ascertain whether a block is protected or unprotected. Verification is performed by inputting the Verify Block Protect command. The Verify Block Protect command, which can be performed simultaneously with operations in another bank, is performed by setting the block address with A0=A6=VIL and A1=VIH. If the block is protected, 01h is output. If the block is unprotected, 00h is output. The status depends on PPB, DPB, WP and ABP and RESET state. Inputting the verify block protect command sequence sets the specified bank to the Verify Block Protect mode. Inputting a Reset command releases this mode and returns the device to Read Mode. When verifying block protect across a bank boundary, a Reset command is needed at the time of the change of a bank. www..com 2008-03-19 F-15/73 256Mbits NOR FLASH MEMORY PAGE 5.18. Hidden ROM Area The TC58FYM8T7D/B7D features a 64-Kwords hidden ROM area, which is separate from the memory cells. The area consists of one block. Data Read, Write and Protect can be performed on this block. Because Protect cannot be released, once the block is protected, data in the block cannot be overwritten. The hidden ROM area is located in the address space indicated in the HIDDEN ROM AREA ADDRESS TABLE. To access the Hidden ROM area, input a Hidden ROM Mode Entry command. The device now enters Hidden ROM Mode, allowing Read, Write, Erase and Block Protect to be executed. Write and Erase operations are the same as auto operations except that the device is in Hidden ROM Mode. To protect the hidden ROM area, use the Hidden ROM Protect Command. The status of Hidden ROM protect operation can be checked by hardware sequence flags. Hidden ROM protect time is equal to tPPRW (Auto PPB set time). The hosts have to decide the protection state of Hidden ROM Area before the PPB Lock has been settled. Once the block has been protected, protection cannot be released. Using Block Protection for Hidden ROM Area must be careful. Note that in Hidden ROM Mode, simultaneous operation cannot be performed for BANK15 in top boot type and for BANK0 in bottom boot type. To exit Hidden ROM Mode, use the Hidden ROM Mode Exit command. This will return the device to Read Mode. HIDDEN ROM AREA ADDRESS TABLE TYPE TC58FYM8T7D TC58FYM8B7D BOOT BLOCK ARCHITECTURE TOP BOOT BLOCK BOTTOM BOOT BLOCK ADDRESS RANGE FF0000h~FFFFFFh 000000h~00FFFFh SIZE 64 Kwords 64 Kwords The Hardware Sequence Flags of the Hidden ROM Protect mode DQ7 DQ6 Toggle 1 Toggle DQ5 0 0 1 DQ4 0 0 0 DQ3 0 0 0 DQ2 1 1 1 DQ1 0 0 0 DQ0 0 0 0 RY/ BY 0 High-Z 0 In Progress Protect Complete Protect Failed 0 1 0 www..com 2008-03-19 F-16/73 256Mbits NOR FLASH MEMORY PAGE 5.21. CFI (Common Flash memory Interface) The TC58FYM8T7D/B7D conforms to the CFI specifications. To read information from the device, input the Query command followed by the address. In Word Mode DQ8~DQ15 all output 0s. To exit this mode, input the Reset command.. CFI CODE TABLE 1 (Continue) ADDRESS A6~A0 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah DATA DQ15~DQ0 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h DESCRIPTION ASCII string "QRY" Primary OEM command set 2: AMD/FJ standard type Address for primary extended table Alternate OEM command set 0: none exists Address for alternate OEM extended table VDD (min) (Write/Erase) DQ7~DQ4: 1 V DQ3~DQ0: 100 mV VDD (max) (Write/Erase) DQ7~DQ4: 1 V DQ3~DQ0: 100 mV VPP (min) voltage VPP (max) voltage Typical time per single word write (2 s) Typical time for minimum size buffer write (2 s) Typical time per individual block erase (2 ms) Typical time for full chip erase (2 ms) Maximum time-out for word write (2 times typical) Maximum time-out for buffer write (2 times typical) Maximum time-out per individual block erase (2 times typical) Maximum time-out for full chip erase (2 times typical) Device Size (2 byte) 1Ah:512Mbit,19h:256Mbit,18h:128Mbit Flash device interface description 1: x 16 Maximum number of bytes in multi-byte write (2 ) N N N N N N N N N N 1Bh 0017h 1Ch 0019h 1Dh 1Eh 1Fh 20h 21h 22h www..com 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h 0019h 0001h 0000h 0004h 0000h 2008-03-19 F-17/73 256Mbits NOR FLASH MEMORY PAGE CFI CODE TABLE 2(Sequel) ADDRESS A6~A0 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 40h 41h 42h 43h 44h DATA DQ15~DQ0 0002h 0007h 0000h 0040h 0000h 00FEh 0000h 0000h 0002h 0050h 0052h 0049h 0031h 0031h DESCRIPTION Number of erase block regions within device Erase Block Region 1 information Bits 0~15: y = block number Bits 16~31: z = block size (z x 256 bytes) Erase Block Region 2 information ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address-Sensitive Unlock 0: Required 1: Not required Erase Suspend 0: Not supported 1: For Read-only 2: For Read & Write Block Protect 0: Not supported X: Number of blocks per group Block Temporary Unprotect 0: Not supported 1: Supported Block Protect/Unprotect scheme Simultaneous operation 0: Not supported 1: Supported Burst Mode 0: Not supported 1: Supported Page Mode 0: Not supported 1: Supported VACC (min) voltage DQ7~DQ4: 1 V DQ3~DQ0: 100 mV VACC (max) voltage DQ7~DQ4: 1 V DQ3~DQ0: 100 mV Top/Bottom Boot Block Flag X = 2: Bottom Boot Block: TC58FYM8B7D X = 3: Top Boot Block: TC58FYM8T7D Program Suspend 0: Not supported 1: Supported 45h 0000h 46h 0002h 47h 0001h 48h 0000h 49h 0007h 4Ah www..com 0001h 4Bh 0000h 4Ch 0001h 4Dh 00B4h 4Eh 00C6h 4Fh 000xh 50h 0001h 2008-03-19 F-18/73 256Mbits NOR FLASH MEMORY PAGE CFI CODE TABLE 3(Sequel) ADDRESS A6~A0 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h DATA DQ15~DQ0 0010h 00XXh 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 00XXh Bank Organization 00h: Data at 4Ah is zero , X: Number of Banks TOP : 10h BOTTOM:17h Bank0 Region information XX: Number of blocks Bank0 DESCRIPTION Bank1 Region information , Number of blocks Bank1 , n=16 Bank2 Region information , Number of blocks Bank2 , n=16 Bank3 Region information , Number of blocks Bank3 , n=16 Bank4 Region information , Number of blocks Bank4 , n=16 Bank5 Region information , Number of blocks Bank5 , n=16 Bank6 Region information , Number of blocks Bank6 , n=16 Bank7 Region information , Number of blocks Bank7 , n=16 Bank8 Region information , Number of blocks Bank8 , n=16 Bank9 Region information , Number of blocks Bank9 , n=16 Bank10 Region information , Number of blocks Bank10 , n=16 Bank11 Region information , Number of blocks Bank11 , n=16 Bank12 Region information , Number of blocks Bank12 , n=16 Bank13 Region information , Number of blocks Bank13 , n=16 Bank14 Region information , Number of blocks Bank14 , n=16 Bank15 Region information XX: Number of blocks Bank15 TOP : 17h BOTTOM:10h www..com 2008-03-19 F-19/73 256Mbits NOR FLASH MEMORY PAGE 5.20. HARDWARE SEQUENCE FLAGS The TC58FYM8T7D/B7D has a Hardware Sequence flag which allows the device status to be determined during an auto mode operation. The output data is read out using the same timing as that used when CE = OE = VIL in Read Mode. The RY/ BY output can be either High or Low. The device re-enters Read Mode automatically after an auto mode operation has been completed successfully. The Hardware Sequence flag is read to determine the device status and the result of the operation is verified by comparing the read-out data with the original data. STATUS Auto Programming/Auto Page Programming Read in Program Suspend In Auto Erase In Progress Selected Read In Erase Suspend Programming Not-selected Auto Programming/Auto Page Programming Time Limit Exceeded Auto Erase Programming in Erase Suspend DQ 7 DQ 7 0 DQ 7 (4) (1) (2) (3) DQ7 DQ 7 (4) DQ6 Toggle Data Toggle Toggle 1 Data Toggle Toggle Toggle Toggle Toggle DQ5 0 Data 0 0 0 Data 0 0 1 1 1 DQ3 0 Data 1 1 0 Data 0 0 0 1 0 DQ2 1 Data Toggle 1 Toggle Data Toggle 1 1 N/A N/A RY/ BY 0 High-Z 0 0 High-Z High-Z 0 0 0 0 0 Data 0 0 1 Data DQ 7 Selected Auto Erase Not-selected Not-selected Selected Notes:DQ outputs cell data and RY/ BY goes High-Impedence when the operation has been completed. DQ0 and DQ1 pins are reserved for future use. 0 is output on DQ0, DQ1 and DQ4. (1) Data output from an address to which Write is being performed is undefined. (2) (3) (4) Output when the block address selected for Auto Block Erase is specified and data is read from there. Output when a block address not selected for Auto Block Erase of same bank as selected block is specified and data is read from there. During Auto Chip Erase, all blocks are selected. In case of Page program operation is program data of (A0, A1, A2) = (1, 1, 1) in eleventh bus write cycle. 5.20.1. DQ7 ( DATA polling ) During an Auto-Program or an Auto-Erase operation, the device status can be determined using the data www..com polling function. DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto-Program operation, DQ7 outputs inverted data during the programming operation and outputs actual data after programming has finished. In an Auto-Erase operation, DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase operation has finished. If an Auto-Program or an Auto-Erase operation fails, DQ7 simply outputs the data. When the operation has finished, the address latch is reset. Data polling is asynchronous with the OE signal. 5.20.2. DQ6 ( Toggle bit 1 ) The device status can be determined by the Toggle Bit function during an Auto-Program or an Auto-Erase operation. The Toggle bit begins toggling on the rising edge of WE in the last bus cycle. DQ6 alternately outputs a 0 or a 1 for each OE access while CE = VIL while the device is busy. When the internal operation has been completed, toggling stops and valid memory cell data can be read by subsequent reading. If the operation fails, the DQ6 output toggles. If an attempt is made to execute an Auto Program operation on a protected block, DQ6 will toggle for around 3 s (typ.). It will then stop toggling. If an attempt is made to execute an Auto Erase operation on a protected block, DQ6 will toggle for around 3 s (typ.). It will then stop toggling. After toggling has stopped the device will return to Read Mode. 2008-03-19 F-20/73 256Mbits NOR FLASH MEMORY PAGE 5.20.3. DQ5 (internal time-out) If an Auto-Program or an Auto-Erase operates normally, DQ5 outputs a 0. If the internal timer times out during a Program or an Erase operation, DQ5 outputs a 1. This indicates that the operation has not been completed within the allotted time. Any attempt to program a 1 into a cell containing a 0 will fail (see Auto-Program Mode). In this case, DQ5 outputs a 1. In this case, DQ5 doesn't indicate defective device but mistaken usage. After an Auto-Program or an Auto-Erase operation ends normally, the device outputs actual cell array data. Therefor only with the data of DQ5 can't specify whether cell array data or hardware sequence flag. The hosts should check the state of device whether progrress or not, using DQ7 or DQ6. In the case of internal time-out, either hardware reset or a software Reset command is required to return the device to Read Mode. 5.20.4. DQ3 (Block Erase timer) DQ3 is used to detect whether in the Auto Erase Mode and the Erase Suspend Mode. The device automatically begins the Erase operation when the command sequence of the Chip Erase or the Block Erase is input, and DQ3 outputs 1. DQ3 outputs 0 to the selection block of the Block Erase at the Erase Suspend Read Mode. DQ3 outputs 0 regardless of the block at the Erase Suspend Program Mode. When DQ3 is a result of an Auto Erase operation failure or outputs 1, and is a result of an Erase Suspend Program failure, DQ3 outputs 0. 5.20.5. DQ2 (Toggle bit 2) DQ2 is used to indicate which blocks have been selected for an Auto Block Erase or to indicate whether the device is in an Erase Suspend Mode. If the data is read continuously from the selected block during an Auto Block Erase, the DQ2 output will toggle. Now 1 will be output from non-selected blocks; thus, the selected block can be ascertained. If the data is read continuously from the block selected for the Auto Block Erase while the device is in the Erase Suspend Mode, the DQ2 output will toggle. Because the DQ6 output is not toggling, it can be determined that the device is in the Erase Suspend Mode. If the data is read from the address to which data is being written during the Erase Suspend in the Programming Mode, DQ2 will output a 1. 5. 20.6. RY/BY (Ready/ BUSY ) The TC58FYM8T7D/B7D has a RY/ BY signal to indicate the device status to the host processor. A 0 (Busy state) indicates that an Auto-Program or an Auto-Erase operation is in progress. A 1 (Ready state) indicates that the operation has finished and that the device can now accept a new command. RY/ BY outputs a 0 when an operation has failed. www..com RY/ BY outputs a 0 after the rising edge of WE in the last command cycle. During an Auto Block Erase operation, commands other than Erase Suspend are ignored. RY/ BY outputs a 1 during an Erase Suspend operation. The output buffer for the RY/ BY pin is an open-drain type circuit, allowing a wired-OR connection. A pull-up resistor must be inserted between VDD and the RY/ BY pin. 2008-03-19 F-21/73 256Mbits NOR FLASH MEMORY PAGE 6. DATA PROTECTION TC58FYM8T7D/B7D includes a function which guards against malfunction or data corruption. 6.1. Protection against Program/Erase Caused by Low Supply Voltage To prevent malfunction at power-on or power-down, the device will not accept commands while VDD is below VLKO. In this state, command input is ignored. If VDD drops below VLKO during an Auto operation, the device will terminate the Auto operation execution. In this case, the Auto operation is not executed again when VDD returns to recommended VDD voltage. Therefore, command need to be input to execute the Auto operation again. 6.2. Protection against Malfunction Caused by Glitches To prevent malfunction write during operation caused by noise from the system, the device will not accept pulses shorter than 3 ns (Typ.) input on WE , CE or OE . However, if a glitch exceeding 3 ns (Typ.) occurs and the glitch is input to the device malfunction write may occur. The device uses standard JEDEC commands. It is conceivable that, in extreme cases, system noise may be misinterpreted as part of a command sequence input and that the device will acknowledge it. Then, even if a proper command is input, the device may not operate. To avoid this possibility, clear the Command Register before command input. In an environment prone to system noise, Toshiba recommends input of a software or hardware reset before command input. 6.3. Protection against Malfunction at Power-on To prevent damage to data caused by sudden noise at power-on, when power is turned on with WE = CE =VIL the device does not latch the command on the first rising edge of WE or CE . Instead, the device automatically Resets the Command Register and enters the Read Mode. 7. AC TEST CONDITIONS PARAMETER Input Pulse Level Input Pulse Rise and Fall Time (10%~90%) Timing Measurement Reference Level (input) www..com Timing Measurement Reference Level (output) Output Load CONDITION VDD, 0.0 V 2ns VDD/2, VDD/2 VDD/2, VDD/2 CL (30 pF) + 1 TTL Gate (AC Test Condition) I/O Z0=50 30pF 50 VDD/2 2008-03-19 F-22/73 256Mbits NOR FLASH MEMORY PAGE 8. AC CHARACTERISTICS AND OPERATING CONDITIONS 8.1. Read Cycle SYMBOL tRC tPRC tACC tCE tOE tPACC tOEH tCEE tOEE tOH tAOH tDF1 tDF2 Read Cycle Time Page Read Cycle Time Address Access Time CE Access Time OE Access Time Page Access Time OE High Level Hold Time (Read) CE to Output Low-Z OE to Output Low-Z Output Data Hold Time Output Data Hold Time (Page Read) CE to Output High-Z OE to Output High-Z PARAMETER MIN 70 15 0 0 0 3 3 MAX 70 70 15 15 12 12 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns www..com 2008-03-19 F-23/73 256Mbits NOR FLASH MEMORY PAGE 8.2. Command Write/Program/Erase cycle SYMBOL tCMD tAS tAH tDS tDH tWELH Command Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time PARAMETER MIN 60 0 20 20 0 MAX UNIT ns ns ns ns ns WE Low-Level Hold Time WE High-Level Hold Time CE Set-up Time to WE Active CE Hold Time from WE High Level CE Low-Level Hold Time CE High-Level Hold Time WE Set-up time to CE Active WE Hold Time from CE High Level OE Set-up Time OE High Level Hold Time (Polling) OE High Level Hold Time (Toggle Read) CE High Level Hold Time (Toggle Read) Address Hold Time (Toggle) Address Set-up Time (Toggle) VDD Set-up Time Program/Erase Valid to RY / BY Delay ( WE Control) ( WE Control) ( WE Control) ( WE Control) ( CE Control) ( CE Control) ( CE Control) ( CE Control) 35 25 0 0 35 25 0 0 0 6 18 18 0 0 500 ns ns ns ns ns ns ns ns ns ns ns ns ns ns s tWEHH tCES tCEH tCELH tCEHH tWES tWEH tOES tOEHP tOEHT tCEHT tAHT tAST tVDS tBUSY 90 500 ns ns ns s s Program Valid to RY / BY Delay during Erase Suspend Mode tRB RY / BY Recovery Time 0 tSUSP Program Suspend Command to Suspend Mode www..com tSUSPA Page Program Suspend Command to Suspend Mode tRESP tSUSE tRESE Program Resume Command to Program Mode Erase Suspend Command to Suspend Mode Erase Resume Command to Erase Mode 7 7 500 25 500 ns s s 2008-03-19 F-24/73 256Mbits NOR FLASH MEMORY PAGE 8.3. Hardware RESET SYMBOL tREADY tREADY tRP tRH PARAMETER Read Mode Recovery Time from RESET (During Auto Operation) Read Mode Recovery Time from RESET (During Non Auto Operation) RESET Low Level Hold Time Recvery Time from RESET MIN MAX 25 500 UNIT s ns ns ns 500 50 8.4. Program and Erase characteristics SYMBOL tPPW tPPAW tPCEW tPBEW tPPRW tPPEW (1) (2) PARAMETER Auto-Program Time (Word Mode) Auto-Page program time (8 word) Auto Chip Erase Time (1) (1) MIN TYP. 12 60 316 1.2 100 2.5 MAX 300 2400 1315 5 (2) UNIT s s s s s Auto Block Erase Time Auto PPB Set Time Auto PPB Clear Time 4000 5000 ms Auto Chip Erase Time and Auto Block Erase Time include internal pre program time. Minimum interval between resume and the following suspend command is 150 s. If it's shorter than 150 s, Auto Block Erase Time expand more than maximum (5.0s). www..com 2008-03-19 F-25/73 256Mbits NOR FLASH MEMORY PAGE 9. TIMING DIAGRAMS VIH or VIL Data invalid Read/ID Read Operation tRC Address tACC tCE CE tOE tOEE OE tCEE WE tOEH tDF2 tDF1 tOH DOUT Hi-Z Output data Valid Hi-Z Page Read Operation Address(A23-3))) tRC Address(2-0) tACC tPRC tPRC tPRC www..com CE tCE tDF1 tOE OE tDF2 WE tOH tPACC tPACC tPACC DOUT Hi-Z DOUT DOUT DOUT DOUT DOUT Hi-Z tAOH tAOH 2008-03-19 F-26/73 256Mbits NOR FLASH MEMORY PAGE Command Write Operation This is the timing of the Command Write Operation. The timing which is described in the following pages is essentially the same as the timing shown on this page. WE Control tCMD Address tAS Command address tAH CE tCES tCEH WE tWELH tDS DIN tVDS VDD tDH tWEHH Command data CE Control tCMD Address Command address tAS tAH www..com CE tCELH tWES WE tDS DIN tVDS VDD tDH tWEH tCEHH Command data 2008-03-19 F-27/73 256Mbits NOR FLASH MEMORY PAGE ID Read Operation (Command Mode) BK + 555h BK + 00h tRC BK + 01h Address 555h tCMD 2AAh CE OE tOES WE tWEHH + tACC DIN AAh 55h 90h Manufacturer code Device code DOUT Hi-Z Read Mode (input of ID Read command sequence) ID Read Mode (Continued) Address 555h tCMD 2AAh 555h CE OE www..com WE DIN AAh 55h F0h DOUT Hi-Z ID Read Mode (input of Reset command sequence) Read Mode Note. BK: Bank address 2008-03-19 F-28/73 256Mbits NOR FLASH MEMORY PAGE Read after command input Command mode Address (1) (2) Asynchronous Read mode Last command address CE OE WE tWEHH + tACC DOUT Last command data Hi-Z Dout valid Hi-Z Notes. 1. Below Commands are objects of above timing. ID Read Command Reset Command in ID Read mode CFI Read Command Reset Command in CFI Read mode Hidden ROM Mode Entry Command Hidden ROM Mode Exit Command Password Verify Command 2. Read Mode after last command mode input change to Read mode , ID read mode , CFI read mode or Hidden Rom mode by Read mode address and Comman mode. Above timming is needed in all cases. www..com 2008-03-19 F-29/73 256Mbits NOR FLASH MEMORY PAGE Auto-Program Operation ( WE Control) Address 555h tCMD 2AAh 555h PA PA CE OE tOES WE tOEHP tPPW DIN AAh 55h A0h PD DOUT tVDS VDD Notes: 1. PA: Program address 2. PD: Program dat Hi-Z DQ7 DOUT www..com 2008-03-19 F-30/73 256Mbits NOR FLASH MEMORY PAGE Auto Page Program Operation ( WE Control) Address (A23-3) tCMD PA PA Address (A2-0) 555h 2AAh 555h 0h 1h 2h 3h 4h 5h 6h 7h 7h CE tOEHP OE tOES tPPAW WE DIN AAh 55h E6h PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 DOUT tVDS Hi-Z DQ7 DOUT www..com VDD Notes: 1. PA: Program address 2.PD: Program Data 2008-03-19 F-31/73 256Mbits NOR FLASH MEMORY PAGE Auto Chip Erase/Auto Block Erase Operation ( WE Control) Address 555h tCMD 2AAh 555h 555h 2AAh 555h/BA CE OE tOES WE DIN tVDS VDD AAh 55h 80h AAh 55h 10h/30h Note. BA: Block address www..com 2008-03-19 F-32/73 256Mbits NOR FLASH MEMORY PAGE Auto Program Operation ( CE Control) Address 555h tCMD 2AAh 555h PA PA CE tPPW OE tOES tOEHP WE DIN AAh 55h A0h PD DOUT tVDS VDD Hi-Z DQ7 DOUT Notes: 1. PA: Program address 2. PD: Program data www..com 2008-03-19 F-33/73 256Mbits NOR FLASH MEMORY PAGE Auto Page Program Operation ( CE Control) Address (A23-3) tCMD Address (A2-0) PA PA 555h 2AAh 555h 0h 1h 2h 3h 4h 5h 6h 7h 7h CE tOEHP OE tOES tPPAW WE DIN AAh 55h E6h PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 DOUT tVDS Hi-Z DQ7 DOUT www..com VDD Notes: 1. PA: Program address 2. PD: Program data 2008-03-19 F-34/73 256Mbits NOR FLASH MEMORY PAGE Auto Chip Erase/Auto Block Erase Operation ( CE Control) Address 555h tCMD 2AAh 555h 555h 2AAh 555h/BA CE OE tOES WE DIN tVDS VDD AAh 55h 80h AAh 55h 10h/30h Note: BA: Block address for Auto Block Erase operation www..com 2008-03-19 F-35/73 256Mbits NOR FLASH MEMORY PAGE Program/Erase Suspend Operation Address BK RA CE OE WE tOE DIN B0h tCE DOUT Hi-Z tSUSP / tSUSPA / tSUSE DOUT Hi-Z RY / BY Program/Erase Mode Suspend Mode Notes: 1. BK: Bank address 2. RA: Read address www..com 2008-03-19 F-36/73 256Mbits NOR FLASH MEMORY PAGE Program/Erase Resume Operation Address RA BK PA/BA CE OE tOES WE tDF1 tDF2 DIN 30h tCE DOUT DOUT Hi-Z Flag Hi-Z tOE tRESP / tRESE RY / BY Suspend Mode Program/Erase Mode Notes: 1. PA: Program address 2. BK: Bank address 3. BA: Block address 4. RA: Read address 5. Flag: Hardware Sequence flag www..com 2008-03-19 F-37/73 256Mbits NOR FLASH MEMORY PAGE RY/BY during Auto Program/Erase Operation CE Command input sequence WE tBUSY During operation RY / BY Hardware Reset Operation (At the Auto Operation) WE tRB RESET tRP tREADY RY / BY Read after RESET tRC Address tRH RESET www..com tACC tOH DOUT Hi-Z Output data valid DOUT Software Reset Operation (At the Auto Operation failure) CE OE tWELH WE tDS DIN F0h tREADY tDH tRB RY / BY 2008-03-19 F-38/73 256Mbits NOR FLASH MEMORY PAGE Hardware Sequence Flag ( DATA Polling) Address Last Command Address tCMD PA/BA CE tCE tOE OE tOEHP WE tPPW / tPCEW / tPBEW DIN Last Command Data tDF1 tDF2 tACC tOH DQ7 DQ7 Valid Valid DQ0~DQ6 tBUSY Invalid Valid Valid At RY / BY Notes. 1. PA: Program address 2. BA: Block address Hardware Sequence Flag (Toggle bit) Address www..com CE tAHT tOEHT tAHT OE tOEH WE tAST tCE tOE DIN Last Command Data DQ6/2 tBUSY Toggle Toggle Toggle Stop* Toggle Valid RY / BY *DQ2/DQ6 stops toggling when auto operation has been completed. 2008-03-19 F-39/73 256Mbits NOR FLASH MEMORY PAGE 10. FLOW CHARTS Auto-Program Start Auto-Program Command Sequence (see below) DATA Polling or Toggle Bit Address = Address + 1 No Last Address? Yes Auto-Program Completed Auto-Program Command Sequence (address/data) 555h/AAh 2AAh/55h 555h/A0h www..com Program Address/ Program Data 2008-03-19 F-40/73 256Mbits NOR FLASH MEMORY PAGE Auto-Page Program START Auto page program command sequence (see below ) DATA Polling or Toggle Bit Address = Address + 1 NO Last address? Yes Auto-Program Completed 555h/AAh 2AAh/55h 555h/E6h Program address (A2=0,A1=0,A0=0) / Program data www..com Program address (A2=0,A1=0,A0=1) / Program data Program address (A2=0,A1=1,A0=0) / Program data Program address (A2=0,A1=1,A0=1) / Program data Program address (A2=1,A1=0,A0=0) / Program data Program address (A2=1,A1=0,A0=1) / Program data Program address (A2=1,A1=1,A0=0) / Program data Program address (A2=1,A1=1,A0=1) / Program data 2008-03-19 F-41/73 256Mbits NOR FLASH MEMORY PAGE Auto Erase Start Auto Erase Command Sequence (see below) DATA Polling or Toggle Bit Auto Erase Completed Auto Chip Erase Command Sequence (address/data) Auto Block Erase Command Sequence (address/data) 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h www..com 555h/10h Block Address/30h 2008-03-19 F-42/73 256Mbits NOR FLASH MEMORY PAGE DQ7 DATA Polling Start Read Byte (DQ0~DQ7) Addr. = VA Yes DQ7 = Data? No No DQ5 = 1? Yes Read Byte (DQ0~DQ7) Addr. = VA 1) 1) : DQ7 must be rechecked even if DQ5 = 1 because DQ7 may change at the same time as DQ5. Yes DQ7 = Data? No Fail Pass DQ6 Toggle Bit Start Read Byte (DQ0~DQ7) Addr. = VA No DQ6 = Toggle? Yes www..com No DQ5 = 1? Yes Read Byte (DQ0~DQ7) Addr. = VA No 1) 1) : DQ6 must be rechecked even if DQ5 = 1 because DQ6 may stop toggling at the same times that DQ5 changes to 1. DQ6 = Toggle? Yes Fail Pass VA: Valid address for programming Any of the addresses within the block being erased during a Block Erase operation "Don't care" during a Chip Erase operation 2008-03-19 F-43/73 256Mbits NOR FLASH MEMORY PAGE Hidden ROM Exit Command Input START 555h/AAh 2AAh/55h 555h/90h 555h/00h FINISH www..com 2008-03-19 F-44/73 256Mbits NOR FLASH MEMORY PAGE Password Protection Mode Locking Set Operation START 555h/AAh 2AAh/55h 555h/60h Password Protection Mode Lock Set th Command sequence 4 bus write cycle (x0A/68h) DATA Polling or Toggle Bit No DQ7 = 1? Yes Hidden ROM Exit Command No DQ5 = 1? Yes Hidden ROM Exit Command Lock Set Complete Device failed www..com 2008-03-19 F-45/73 256Mbits NOR FLASH MEMORY PAGE Password Program Operation START PWA = 0 555h/AAh 2AAh/55h 555h/38h PWA = PWA +1 Password Program Command Sequence 4th Bus Write Cycle (PWA/PD) DATA Polling or Toggle Bit No DQ7 = 1? Yes Hidden ROM Exit Command No DQ5 = 1? Yes Hidden ROM Exit Command No PWA = 3? Yes Password Program Complete Device Failed www..com PWA/PD: Password Address / Password Program Data - XX0h/PD0 (PD0: Data of 1-16 bits in password (64bits) - XX1h/PD1 (PD1: Data of 17-32 bits in password (64bits) - XX2h/PD2 (PD2: Data of 33-48 bits in password (64bits) - XX3h/PD3 (PD3: Data of 49-64 bits in password (64bits) 2008-03-19 F-46/73 256Mbits NOR FLASH MEMORY PAGE Password Verify Operation START 555h/AAh 2AAh/55h 555h/C8h Read Password 1 0 (x0h/PWD) Read Password 1 (x1h/PWD) Read Password 2 (x2h/PWD) Read Password 3 (x3h/PWD) Hidden ROM Exit Command Password Verify Complete www..com PWD: Password Output Data PDW0: Data of 1-16 bits in password (64bits) PDW1: Data of 17-32 bits in password (64bits) PDW2: Data of 33-48 bits in password (64bits) PDW3: Data of 49-64 bits in password (64bits) 2008-03-19 F-47/73 256Mbits NOR FLASH MEMORY PAGE Password Unlock Command Operation START 555h/AAh 2AAh/55h 555h/28h Read Password 0 Write 1 (x0h/PWD0) (x0h/PWD) Wait 2us or DQ6= No Toggle? Write Password 1 (x1h/PWD1) Wait 2us or DQ6= No Toggle? Write Password 2 (x2h/PWD2) Wait 2us or DQ6= No Toggle? Write Password 3 (x3h/PWD3) www..com Wait 2us DQ7=1 or DQ6= No Toggle? Hidden ROM Exit Command Password Unlock Complete 2008-03-19 F-48/73 256Mbits NOR FLASH MEMORY PAGE Non-Password Protection Mode Locking Set Operation START 555h/AAh 2AAh/55h 555h/60h Non Password Protection Mode Lock Set Command Sequence 4 th bus write cycle (x12/68h) DATA Polling, Toggle Bit No DQ7 = 1? Yes Hidden ROM Exit Command No DQ5 = 1? Yes Hidden ROM Exit Command Lock set complete Device failed www..com 2008-03-19 F-49/73 256Mbits NOR FLASH MEMORY PAGE PPB Set Command Sequence START 555h/AAh 2AAh/55h 555h/60h PPB Set Command Sequence th 4 bus write cycle (BA+02h/68h) DATA Polling or Toggle bit No DQ7 = 1? Yes Hidden ROM Exit Command No DQ5 = 1? Yes Hidden ROM Exit Command Block protect complete Device failed www..com 2008-03-19 F-50/73 256Mbits NOR FLASH MEMORY PAGE PPB Clear Command Sequence START 555h/AAh 2AAh/55h 555h/60h PPB Clear Command Sequence 4 bus write Cycle (xx02h/60h) th DATA Polling or Toggle Bit No DQ7 = 1? Yes Hidden ROM Exit Command No DQ5 = 1? Yes Hidden ROM Exit Command PPB Clear Complete Device failed www..com 2008-03-19 F-51/73 256Mbits NOR FLASH MEMORY PAGE PPB Lock Operation PPB Lock Set START PPB Lock Verify START 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/78h 555h/58h Hidden ROM Exit Command PPB Lock Verify PPB Lock Verify DQ1=1:PPB Lock Set DQ1=0: PPB Lock is cleared Hidden ROM Exit Command Hidden ROM Exit Command Lock Set Complete Complete PPB Lock Clear START www..com Power On or RESET = VIL Complete 2008-03-19 F-52/73 256Mbits NOR FLASH MEMORY PAGE DPB Command Operation DPB Set START DPB Verify START 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/48h 555h/58h BA/x1h Verify DPB(Add = BA) DQ0=1: DPP set DQ0=0: DPP is cleared Yes Protect Another Block? No Hidden ROM Exit Command Yes Check Another Block? No Hidden ROM Exit Command DPB Set Complete Verify Complete DPB Clear 1 www..com START DPB Clear 2 START 555h/AAh 2AAh/55h Powe On or RESET = VIL DPB Clear Complete 555h/48h BA/00h Yes Erase Another Block? No Hidden ROM Exit Command DPB Clear Complete 2008-03-19 F-53/73 256Mbits NOR FLASH MEMORY PAGE 11. BLOCK ADDRESS TABLES * : VIH or VIL 11.1. TC58FYM8T7D (Top boot block) 1/9 Block Address Bank # Block Bank Address # A23 BA0 BA1 BA2 BA3 BA4 BA5 BA6 BK0 BA7 BA8 BA9 BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A22 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A21 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A20 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H A19 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H A18 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H A17 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H A16 L H L H L H L H L H L H L H L H L H L H L H L H L L H H L L H H A15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Word mode 000000h~00FFFFh 010000h~01FFFFh 020000h~02FFFFh 030000h~03FFFFh 040000h~04FFFFh 050000h~05FFFFh 060000h~06FFFFh 070000h~07FFFFh 080000h~08FFFFh 090000h~09FFFFh 0A0000h~0AFFFFh 0B0000h~0BFFFFh 0C0000h~0CFFFFh 0D0000h~0DFFFFh 0E0000h~0EFFFFh 0F0000h~0FFFFFh 100000h~10FFFFh 110000h~11FFFFh 120000h~12FFFFh 130000h~13FFFFh 140000h~14FFFFh 150000h~15FFFFh 160000h~16FFFFh 170000h~17FFFFh 180000h~18FFFFh 190000h~19FFFFh 1A0000h~1AFFFFh 1B0000h~1BFFFFh 1C0000h~1CFFFFh 1D0000h~1DFFFFh 1E0000h~1EFFFFh 1F0000h~1FFFFFh Address Range www..com BA18 BA19 BA20 BA21 BA22 BA23 BK1 BA24 BA25 BA26 BA27 BA28 BA29 BA30 BA31 2008-03-19 F-54/73 256Mbits NOR FLASH MEMORY PAGE 11.1. TC58FYM8T7D (Top boot block) 2/9 Block Address Bank # Block Bank Address # A23 BA32 BA33 BA34 BA35 BA36 BA37 BA38 BA39 BK2 BA40 BA41 BA42 BA43 BA44 BA45 BA46 BA47 BA48 BA49 BA50 BA51 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 280000h~28FFFFh 290000h~29FFFFh 2A0000h~2AFFFFh 2B0000h~2BFFFFh 2C0000h~2CFFFFh 2D0000h~2DFFFFh 2E0000h~2EFFFFh 2F0000h~2FFFFFh 300000h~30FFFFh 310000h~31FFFFh 320000h~32FFFFh 330000h~33FFFFh 340000h~34FFFFh 350000h~35FFFFh 360000h~36FFFFh 370000h~37FFFFh 380000h~38FFFFh 390000h~39FFFFh 3A0000h~3AFFFFh 3B0000h~3BFFFFh 3C0000h~3CFFFFh 3D0000h~3DFFFFh 3E0000h~3EFFFFh 3F0000h~3FFFFFh L L L L L L L L A22 L L L L L L L L A21 H H H H H H H H A20 L L L L L L L L A19 L L L L L L L L A18 L L L L H H H H A17 L L H H L L H H A16 L H L H L H L H A15 * * * * * * * * A14 * * * * * * * * A13 * * * * * * * * Word mode 200000h~20FFFFh 210000h~21FFFFh 220000h~22FFFFh 230000h~23FFFFh 240000h~24FFFFh 250000h~25FFFFh 260000h~26FFFFh 270000h~27FFFFh Address Range www..com BA52 BA53 BA54 BA55 BK3 BA56 BA57 BA58 BA59 BA60 BA61 BA62 BA63 2008-03-19 F-55/73 256Mbits NOR FLASH MEMORY PAGE 11.1. TC58FYM8T7D (Top boot block) 3/9 Block Address Bank # Block Bank Address # A23 BA64 BA65 BA66 BA67 BA68 BA69 BA70 BA71 BK4 BA72 BA73 BA74 BA75 BA76 BA77 BA78 BA79 BA80 BA81 BA82 BA83 L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L A22 H H H H H H H H A21 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A20 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H A19 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H A18 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H A17 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H A16 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H A15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Word mode 400000h~40FFFFh 410000h~41FFFFh 420000h~42FFFFh 430000h~43FFFFh 440000h~44FFFFh 450000h~45FFFFh 460000h~46FFFFh 470000h~47FFFFh 480000h~48FFFFh 490000h~49FFFFh 4A0000h~4AFFFFh 4B0000h~4BFFFFh 4C0000h~4CFFFFh 4D0000h~4DFFFFh 4E0000h~4EFFFFh 4F0000h~4FFFFFh 500000h~50FFFFh 510000h~51FFFFh 520000h~52FFFFh 530000h~53FFFFh 540000h~54FFFFh 550000h~55FFFFh 560000h~56FFFFh 570000h~57FFFFh 580000h~58FFFFh 590000h~59FFFFh 5A0000h~5AFFFFh 5B0000h~5BFFFFh 5C0000h~5CFFFFh 5D0000h~5DFFFFh 5E0000h~5EFFFFh 5F0000h~5FFFFFh Address Range www..com BA84 BA85 BA86 BA87 BK5 BA88 BA89 BA90 BA91 BA92 BA93 BA94 BA95 2008-03-19 F-56/73 256Mbits NOR FLASH MEMORY PAGE 11.1. TC58FYM8T7D (Top boot block) 4/9 Block Address Bank # Block Bank Address # A23 BA96 BA97 BA98 BA99 BA100 BA101 BA102 BA103 BK6 BA104 BA105 BA106 BA107 BA108 BA109 BA110 BA111 BA112 BA113 BA114 BA115 L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 680000h~68FFFFh 690000h~69FFFFh 6A0000h~6AFFFFh 6B0000h~6BFFFFh 6C0000h~6CFFFFh 6D0000h~6DFFFFh 6E0000h~6EFFFFh 6F0000h~6FFFFFh 700000h~70FFFFh 710000h~71FFFFh 720000h~72FFFFh 730000h~73FFFFh 740000h~74FFFFh 750000h~75FFFFh 760000h~76FFFFh 770000h~77FFFFh 780000h~78FFFFh 790000h~79FFFFh 7A0000h~7AFFFFh 7B0000h~7BFFFFh 7C0000h~7CFFFFh 7D0000h~7DFFFFh 7E0000h~7EFFFFh 7F0000h~7FFFFFh L L L L L L L L A22 H H H H H H H H A21 H H H H H H H H A20 L L L L L L L L A19 L L L L L L L L A18 L L L L H H H H A17 L L H H L L H H A16 L H L H L H L H A15 * * * * * * * * A14 * * * * * * * * A13 * * * * * * * * Word mode 600000h~60FFFFh 610000h~61FFFFh 620000h~62FFFFh 630000h~63FFFFh 640000h~64FFFFh 650000h~65FFFFh 660000h~66FFFFh 670000h~67FFFFh Address Range www..com BA116 BA117 BA118 BA119 BK7 BA120 BA121 BA122 BA123 BA124 BA125 BA126 BA127 2008-03-19 F-57/73 256Mbits NOR FLASH MEMORY PAGE 11.1. TC58FYM8T7D (Top boot block) 5/9 Block Address Bank # Block Bank Address # A23 BA128 BA129 BA130 BA131 BA132 BA133 BA134 BA135 BK8 BA136 BA137 BA138 BA139 BA140 BA141 BA142 BA143 BA144 BA145 BA146 BA147 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A22 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A21 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A20 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H A19 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H A18 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H A17 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H A16 L H L H L H L H L H L H L H L H L H L H L H L H L L H H L L H H A15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Word mode 800000h~80FFFFh 810000h~81FFFFh 820000h~82FFFFh 830000h~83FFFFh 840000h~84FFFFh 850000h~85FFFFh 860000h~86FFFFh 870000h~87FFFFh 880000h~88FFFFh 890000h~89FFFFh 8A0000h~8AFFFFh 8B0000h~8BFFFFh 8C0000h~8CFFFFh 8D0000h~8DFFFFh 8E0000h~8EFFFFh 8F0000h~8FFFFFh 900000h~90FFFFh 910000h~91FFFFh 920000h~92FFFFh 930000h~93FFFFh 940000h~94FFFFh 950000h~95FFFFh 960000h~96FFFFh 970000h~97FFFFh 980000h~98FFFFh 990000h~99FFFFh 9A0000h~9AFFFFh 9B0000h~9BFFFFh 9C0000h~9CFFFFh 9D0000h~9DFFFFh 9E0000h~9EFFFFh 9F0000h~9FFFFFh Address Range www..com BA148 BA149 BA150 BA151 BK9 BA152 BA153 BA154 BA155 BA156 BA157 BA158 BA159 2008-03-19 F-58/73 256Mbits NOR FLASH MEMORY PAGE 11.1. TC58FYM8T7D (Top boot block) 6/9 Block Address Bank # Block Bank Address # A23 BA160 BA161 BA162 BA163 BA164 BA165 BA166 BA167 BK10 BA168 BA169 BA170 BA171 BA172 BA173 BA174 BA175 BA176 BA177 BA178 BA179 H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A80000h~A8FFFFh A90000h~A9FFFFh AA0000h~AAFFFFh AB0000h~ABFFFFh AC0000h~ACFFFFh AD0000h~ADFFFFh AE0000h~AEFFFFh AF0000h~AFFFFFh B00000h~B0FFFFh B10000h~B1FFFFh B20000h~B2FFFFh B30000h~B3FFFFh B40000h~B4FFFFh B50000h~B5FFFFh B60000h~B6FFFFh B70000h~B7FFFFh B80000h~B8FFFFh B90000h~B9FFFFh BA0000h~BAFFFFh BB0000h~BBFFFFh BC0000h~BCFFFFh BD0000h~BDFFFFh BE0000h~BEFFFFh BF0000h~BFFFFFh H H H H H H H H A22 L L L L L L L L A21 H H H H H H H H A20 L L L L L L L L A19 L L L L L L L L A18 L L L L H H H H A17 L L H H L L H H A16 L H L H L H L H A15 * * * * * * * * A14 * * * * * * * * A13 * * * * * * * * Word mode A00000h~A0FFFFh A10000h~A1FFFFh A20000h~A2FFFFh A30000h~A3FFFFh A40000h~A4FFFFh A50000h~A5FFFFh A60000h~A6FFFFh A70000h~A7FFFFh Address Range www..com BA180 BA181 BA182 BA183 BK11 BA184 BA185 BA186 BA187 BA188 BA189 BA190 BA191 2008-03-19 F-59/73 256Mbits NOR FLASH MEMORY PAGE 11.1. TC58FYM8T7D (Top boot block) 7/9 Block Address Bank # Block Bank Address # A23 BA192 BA193 BA194 BA195 BA196 BA197 BA198 BA199 BK12 BA200 BA201 BA202 BA203 BA204 BA205 BA206 BA207 BA208 BA209 BA210 BA211 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C80000h~C8FFFFh C90000h~C9FFFFh CA0000h~CAFFFFh CB0000h~CBFFFFh CC0000h~CCFFFFh CD0000h~CDFFFFh CE0000h~CEFFFFh CF0000h~CFFFFFh D00000h~D0FFFFh D10000h~D1FFFFh D20000h~D2FFFFh D30000h~D3FFFFh D40000h~D4FFFFh D50000h~D5FFFFh D60000h~D6FFFFh D70000h~D7FFFFh D80000h~D8FFFFh D90000h~D9FFFFh DA0000h~DAFFFFh DB0000h~DBFFFFh DC0000h~DCFFFFh DD0000h~DDFFFFh DE0000h~DEFFFFh DF0000h~DFFFFFh H H H H H H H H A22 H H H H H H H H A21 L L L L L L L L A20 L L L L L L L L A19 L L L L L L L L A18 L L L L H H H H A17 L L H H L L H H A16 L H L H L H L H A15 * * * * * * * * A14 * * * * * * * * A13 * * * * * * * * Word mode C00000h~C0FFFFh C10000h~C1FFFFh C20000h~C2FFFFh C30000h~C3FFFFh C40000h~C4FFFFh C50000h~C5FFFFh C60000h~C6FFFFh C70000h~C7FFFFh Address Range www..com BA212 BA213 BA214 BA215 BK13 BA216 BA217 BA218 BA219 BA220 BA221 BA222 BA223 2008-03-19 F-60/73 256Mbits NOR FLASH MEMORY PAGE 11.1. TC58FYM8T7D (Top boot block) 8/9 Block Address Bank # Block Bank Address # A23 BA224 BA225 BA226 BA227 BA228 BA229 BA230 BA231 BK14 BA232 BA233 BA234 BA235 BA236 BA237 BA238 BA239 BA240 BA241 BA242 BA243 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H L L L L H H H H L L L L H H H H L L L L H H H L L H H L L H H L L H H L L H H L L H H L L H L H L H L H L H L H L H L H L H L H L H L H L * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * E80000h~E8FFFFh E90000h~E9FFFFh EA0000h~EAFFFFh EB0000h~EBFFFFh EC0000h~ECFFFFh ED0000h~EDFFFFh EE0000h~EEFFFFh EF0000h~EFFFFFh F00000h~F0FFFFh F10000h~F1FFFFh F20000h~F2FFFFh F30000h~F3FFFFh F40000h~F4FFFFh F50000h~F5FFFFh F60000h~F6FFFFh F70000h~F7FFFFh F80000h~F8FFFFh F90000h~F9FFFFh FA0000h~FAFFFFh FB0000h~FBFFFFh FC0000h~FCFFFFh FD0000h~FDFFFFh FE0000h~FEFFFFh H H H H H H H H A22 H H H H H H H H A21 H H H H H H H H A20 L L L L L L L L A19 L L L L L L L L A18 L L L L H H H H A17 L L H H L L H H A16 L H L H L H L H A15 * * * * * * * * A14 * * * * * * * * A13 * * * * * * * * Word mode E00000h~E0FFFFh E10000h~E1FFFFh E20000h~E2FFFFh E30000h~E3FFFFh E40000h~E4FFFFh E50000h~E5FFFFh E60000h~E6FFFFh E70000h~E7FFFFh Address Range www..com BA244 BA245 BA246 BA15 BA247 BA248 BA249 BA250 BA251 BA252 BA253 BA254 2008-03-19 F-61/73 256Mbits NOR FLASH MEMORY PAGE 11.1. TC58FYM8T7D (Top boot block) 9/9 Block Address Bank # Block Bank Address # A23 BA255 BA256 BA257 BA258 BK15 BA259 BA260 BA261 BA262 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L H H L H L H FF8000h~FF9FFFh FFA000h~FFBFFFh FFC000h~FFDFFFh FFE000h~FFFFFFh H H H H A22 H H H H A21 H H H H A20 H H H H A19 H H H H A18 H H H H A17 H H H H A16 H H H H A15 L L L L A14 L L H H A13 L H L H Word mode FF0000h~FF1FFFh FF2000h~FF3FFFh FF4000h~FF5FFFh FF6000h~FF7FFFh Address Range www..com 2008-03-19 F-62/73 256Mbits NOR FLASH MEMORY PAGE 11.2. TC58FYM8B7D (Bottom boot block) 1/9 Block Address Bank # Block Bank Address # A23 BA0 BA1 BA2 BK0 BA3 BA4 BA5 BA6 BA7 L L L L L L L L A22 L L L L L L L L A21 L L L L L L L L A20 L L L L L L L L A19 L L L L L L L L A18 L L L L L L L L A17 L L L L L L L L A16 L L L L L L L L A15 L L L L H H H H A14 L L H H L L H H A13 L H L H L H L H Word mode 000000h~001FFFh 002000h~003FFFh 004000h~005FFFh 006000h~007FFFh 008000h~009FFFh 00A000h~00BFFFh 00C000h~00DFFFh 00E000h~00FFFFh Address Range www..com 2008-03-19 F-63/73 256Mbits NOR FLASH MEMORY PAGE 11.2. TC58FYM8B7D (Bottom boot block) 2/9 Block Address Bank # Block Bank Address # A23 BA8 BA9 BA10 BA11 BA12 BA13 BA14 BK0 BA15 BA16 BA17 BA18 BA19 BA20 BA21 BA22 BA23 BA24 BA25 BA26 BA27 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A22 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A21 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A20 L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H A19 L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H A18 L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H A17 L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H A16 H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H A15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Word mode 010000h~01FFFFh 020000h~02FFFFh 030000h~03FFFFh 040000h~04FFFFh 050000h~05FFFFh 060000h~06FFFFh 070000h~07FFFFh 080000h~08FFFFh 090000h~09FFFFh 0A0000h~0AFFFFh 0B0000h~0BFFFFh 0C0000h~0CFFFFh 0D0000h~0DFFFFh 0E0000h~0EFFFFh 0F0000h~0FFFFFh 100000h~10FFFFh 110000h~11FFFFh 120000h~12FFFFh 130000h~13FFFFh 140000h~14FFFFh 150000h~15FFFFh 160000h~16FFFFh 170000h~17FFFFh 180000h~18FFFFh 190000h~19FFFFh 1A0000h~1AFFFFh 1B0000h~1BFFFFh 1C0000h~1CFFFFh 1D0000h~1DFFFFh 1E0000h~1EFFFFh 1F0000h~1FFFFFh Address Range www..com BA28 BA29 BA30 BK1 BA31 BA32 BA33 BA34 BA35 BA36 BA37 BA38 2008-03-19 F-64/73 256Mbits NOR FLASH MEMORY PAGE 11.2. TC58FYM8B7D (Bottom boot block) 3/9 Block Address Bank # Block Bank Address # A23 BA39 BA40 BA41 BA42 BA43 BA44 BA45 BA46 BK2 BA47 BA48 BA49 BA50 BA51 BA52 BA53 BA54 BA55 BA56 BA57 BA58 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 280000h~28FFFFh 290000h~29FFFFh 2A0000h~2AFFFFh 2B0000h~2BFFFFh 2C0000h~2CFFFFh 2D0000h~2DFFFFh 2E0000h~2EFFFFh 2F0000h~2FFFFFh 300000h~30FFFFh 310000h~31FFFFh 320000h~32FFFFh 330000h~33FFFFh 340000h~34FFFFh 350000h~35FFFFh 360000h~36FFFFh 370000h~37FFFFh 380000h~38FFFFh 390000h~39FFFFh 3A0000h~3AFFFFh 3B0000h~3BFFFFh 3C0000h~3CFFFFh 3D0000h~3DFFFFh 3E0000h~3EFFFFh 3F0000h~3FFFFFh L L L L L L L L A22 L L L L L L L L A21 H H H H H H H H A20 L L L L L L L L A19 L L L L L L L L A18 L L L L H H H H A17 L L H H L L H H A16 L H L H L H L H A15 * * * * * * * * A14 * * * * * * * * A13 * * * * * * * * Word mode 200000h~20FFFFh 210000h~21FFFFh 220000h~22FFFFh 230000h~23FFFFh 240000h~24FFFFh 250000h~25FFFFh 260000h~26FFFFh 270000h~27FFFFh Address Range www..com BA59 BA60 BA61 BA62 BK3 BA63 BA64 BA65 BA66 BA67 BA68 BA69 BA70 2008-03-19 F-65/73 256Mbits NOR FLASH MEMORY PAGE 11.2. TC58FYM8B7D (Bottom boot block) 4/9 Block Address Bank # Block Bank Address # A23 BA71 BA72 BA73 BA74 BA75 BA76 BA77 BA78 BK4 BA79 BA80 BA81 BA82 BA83 BA84 BA85 BA86 BA87 BA88 BA89 BA90 L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 480000h~48FFFFh 490000h~49FFFFh 4A0000h~4AFFFFh 4B0000h~4BFFFFh 4C0000h~4CFFFFh 4D0000h~4DFFFFh 4E0000h~4EFFFFh 4F0000h~4FFFFFh 500000h~50FFFFh 510000h~51FFFFh 520000h~52FFFFh 530000h~53FFFFh 540000h~54FFFFh 550000h~55FFFFh 560000h~56FFFFh 570000h~57FFFFh 580000h~58FFFFh 590000h~59FFFFh 5A0000h~5AFFFFh 5B0000h~5BFFFFh 5C0000h~5CFFFFh 5D0000h~5DFFFFh 5E0000h~5EFFFFh 5F0000h~5FFFFFh L L L L L L L L A22 H H H H H H H H A21 L L L L L L L L A20 L L L L L L L L A19 L L L L L L L L A18 L L L L H H H H A17 L L H H L L H H A16 L H L H L H L H A15 * * * * * * * * A14 * * * * * * * * A13 * * * * * * * * Word mode 400000h~40FFFFh 410000h~41FFFFh 420000h~42FFFFh 430000h~43FFFFh 440000h~44FFFFh 450000h~45FFFFh 460000h~46FFFFh 470000h~47FFFFh Address Range www..com BA91 BA92 BA93 BA94 BK5 BA95 BA96 BA97 BA98 BA99 BA100 BA101 BA102 2008-03-19 F-66/73 256Mbits NOR FLASH MEMORY PAGE 11.2. TC58FYM8B7D (Bottom boot block) 5/9 Block Address Bank # Block Bank Address # A23 BA103 BA104 BA105 BA106 BA107 BA108 BA109 BA110 BK6 BA111 BA112 BA113 BA114 BA115 BA116 BA117 BA118 BA119 BA120 BA121 BA122 L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 680000h~68FFFFh 690000h~69FFFFh 6A0000h~6AFFFFh 6B0000h~6BFFFFh 6C0000h~6CFFFFh 6D0000h~6DFFFFh 6E0000h~6EFFFFh 6F0000h~6FFFFFh 700000h~70FFFFh 710000h~71FFFFh 720000h~72FFFFh 730000h~73FFFFh 740000h~74FFFFh 750000h~75FFFFh 760000h~76FFFFh 770000h~77FFFFh 780000h~78FFFFh 790000h~79FFFFh 7A0000h~7AFFFFh 7B0000h~7BFFFFh 7C0000h~7CFFFFh 7D0000h~7DFFFFh 7E0000h~7EFFFFh 7F0000h~7FFFFFh L L L L L L L L A22 H H H H H H H H A21 H H H H H H H H A20 L L L L L L L L A19 L L L L L L L L A18 L L L L H H H H A17 L L H H L L H H A16 L H L H L H L H A15 * * * * * * * * A14 * * * * * * * * A13 * * * * * * * * Word mode 600000h~60FFFFh 610000h~61FFFFh 620000h~62FFFFh 630000h~63FFFFh 640000h~64FFFFh 650000h~65FFFFh 660000h~66FFFFh 670000h~67FFFFh Address Range www..com BA123 BA124 BA125 BA126 BK7 BA127 BA128 BA129 BA130 BA131 BA132 BA133 BA134 2008-03-19 F-67/73 256Mbits NOR FLASH MEMORY PAGE 11.2. TC58FYM8B7D (Bottom boot block) 6/9 Block Address Bank # Block Bank Address # A23 BA135 BA136 BA137 BA138 BA139 BA140 BA141 BA142 BK8 BA143 BA144 BA145 BA146 BA147 BA148 BA149 BA150 BA151 BA152 BA153 BA154 H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 880000h~88FFFFh 890000h~89FFFFh 8A0000h~8AFFFFh 8B0000h~8BFFFFh 8C0000h~8CFFFFh 8D0000h~8DFFFFh 8E0000h~8EFFFFh 8F0000h~8FFFFFh 900000h~90FFFFh 910000h~91FFFFh 920000h~92FFFFh 930000h~93FFFFh 940000h~94FFFFh 950000h~95FFFFh 960000h~96FFFFh 970000h~97FFFFh 980000h~98FFFFh 990000h~99FFFFh 9A0000h~9AFFFFh 9B0000h~9BFFFFh 9C0000h~9CFFFFh 9D0000h~9DFFFFh 9E0000h~9EFFFFh 9F0000h~9FFFFFh H H H H H H H H A22 L L L L L L L L A21 L L L L L L L L A20 L L L L L L L L A19 L L L L L L L L A18 L L L L H H H H A17 L L H H L L H H A16 L H L H L H L H A15 * * * * * * * * A14 * * * * * * * * A13 * * * * * * * * Word mode 800000h~80FFFFh 810000h~81FFFFh 820000h~82FFFFh 830000h~83FFFFh 840000h~84FFFFh 850000h~85FFFFh 860000h~86FFFFh 870000h~87FFFFh Address Range www..com BA155 BA156 BA157 BA158 BK9 BA159 BA160 BA161 BA162 BA163 BA164 BA165 BA166 2008-03-19 F-68/73 256Mbits NOR FLASH MEMORY PAGE 11.2. TC58FYM8B7D (Bottom boot block) 7/9 Block Address Bank # Block Bank Address # A23 BA167 BA168 BA169 BA170 BA171 BA172 BA173 BK10 BA174 BA175 BA176 BA177 BA178 BA179 BA180 BA181 BA182 BA183 BA184 BA185 BA186 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A22 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A21 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A20 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H A19 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H A18 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H A17 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H A16 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H A15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Word mode A00000h~A0FFFFh A10000h~A1FFFFh A20000h~A2FFFFh A30000h~A3FFFFh A40000h~A4FFFFh A50000h~A5FFFFh A60000h~A6FFFFh A70000h~A7FFFFh A80000h~A8FFFFh A90000h~A9FFFFh AA0000h~AAFFFFh AB0000h~ABFFFFh AC0000h~ACFFFFh AD0000h~ADFFFFh AE0000h~AEFFFFh AF0000h~AFFFFFh B00000h~B0FFFFh B10000h~B1FFFFh B20000h~B2FFFFh B30000h~B3FFFFh B40000h~B4FFFFh B50000h~B5FFFFh B60000h~B6FFFFh B70000h~B7FFFFh B80000h~B8FFFFh B90000h~B9FFFFh BA0000h~BAFFFFh BB0000h~BBFFFFh BC0000h~BCFFFFh BD0000h~BDFFFFh BE0000h~BEFFFFh BF0000h~BFFFFFh Address Range www..com BA187 BA188 BA189 BA190 BK11 BA191 BA192 BA193 BA194 BA195 BA196 BA197 BA198 2008-03-19 F-69/73 256Mbits NOR FLASH MEMORY PAGE 11.2. TC58FYM8B7D (Bottom boot block) 8/9 Block Address Bank # Block Bank Address # A23 BA199 BA200 BA201 BA202 BA203 BA204 BA205 BA206 BK12 BA207 BA208 BA209 BA210 BA211 BA212 BA213 BA214 BA215 BA216 BA217 BA218 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C80000h~C8FFFFh C90000h~C9FFFFh CA0000h~CAFFFFh CB0000h~CBFFFFh CC0000h~CCFFFFh CD0000h~CDFFFFh CE0000h~CEFFFFh CF0000h~CFFFFFh D00000h~D0FFFFh D10000h~D1FFFFh D20000h~D2FFFFh D30000h~D3FFFFh D40000h~D4FFFFh D50000h~D5FFFFh D60000h~D6FFFFh D70000h~D7FFFFh D80000h~D8FFFFh D90000h~D9FFFFh DA0000h~DAFFFFh DB0000h~DBFFFFh DC0000h~DCFFFFh DD0000h~DDFFFFh DE0000h~DEFFFFh DF0000h~DFFFFFh H H H H H H H H A22 H H H H H H H H A21 L L L L L L L L A20 L L L L L L L L A19 L L L L L L L L A18 L L L L H H H H A17 L L H H L L H H A16 L H L H L H L H A15 * * * * * * * * A14 * * * * * * * * A13 * * * * * * * * Word mode C00000h~C0FFFFh C10000h~C1FFFFh C20000h~C2FFFFh C30000h~C3FFFFh C40000h~C4FFFFh C50000h~C5FFFFh C60000h~C6FFFFh C70000h~C7FFFFh Address Range www..com BA219 BA220 BA221 BA222 BK13 BA223 BA224 BA225 BA226 BA227 BA228 BA229 BA230 2008-03-19 F-70/73 256Mbits NOR FLASH MEMORY PAGE 11.2. TC58FYM8B7D (Bottom boot block) 9/9 Block Address Bank # Block Bank Address # A23 BA231 BA232 BA233 BA234 BA235 BA236 BA237 BK14 BA238 BA239 BA240 BA241 BA242 BA243 BA244 BA245 BA246 BA247 BA248 BA249 BA250 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A22 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A21 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A20 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H A19 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H A18 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H A17 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H A16 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H A15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Word mode E00000h~E0FFFFh E10000h~E1FFFFh E20000h~E2FFFFh E30000h~E3FFFFh E40000h~E4FFFFh E50000h~E5FFFFh E60000h~E6FFFFh E70000h~E7FFFFh E80000h~E8FFFFh E90000h~E9FFFFh EA0000h~EAFFFFh EB0000h~EBFFFFh EC0000h~ECFFFFh ED0000h~EDFFFFh EE0000h~EEFFFFh EF0000h~EFFFFFh F00000h~F0FFFFh F10000h~F1FFFFh F20000h~F2FFFFh F30000h~F3FFFFh F40000h~F4FFFFh F50000h~F5FFFFh F60000h~F6FFFFh F70000h~F7FFFFh F80000h~F8FFFFh F90000h~F9FFFFh FA0000h~FAFFFFh FB0000h~FBFFFFh FC0000h~FCFFFFh FD0000h~FDFFFFh FE0000h~FEFFFFh FF0000h~FFFFFFh Address Range www..com BA251 BA252 BA253 BA254 BK15 BA255 BA256 BA257 BA258 BA259 BA260 BA261 BA262 2008-03-19 F-71/73 256Mbits NOR FLASH MEMORY PAGE 12. BLOCK SIZE TABLE 12.1. TC58FYM8T7D (Top boot block) Block # BA0~BA15 BA16~BA31 BA32~BA47 BA48~BA63 BA64~BA79 BA80~BA95 BA96~BA111 BA112~BA127 BA128~BA143 BA144~BA159 BA160~BA175 BA176~BA191 BA192~BA207 BA208~BA223 BA224~BA239 BA240~BA254 BA255~BA262 Block size 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 15 8Kwords x 8 BK15 1024Kwords 23 Bank # BK0 BK1 BK2 BK3 BK4 BK5 BK6 BK7 BK8 BK9 BK10 BK11 BK12 BK13 BK14 Bank size 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords Number of block 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 www..com 2008-03-19 F-72/73 256Mbits NOR FLASH MEMORY PAGE 12.2. TC58FYM8B7D (Bottom boot block) Block # BA0~BA7 BA8~BA22 BA23~BA38 BA39~BA54 BA55~BA70 BA71~BA86 BA87~BA102 BA103~BA118 BA119~BA134 BA135~BA150 BA151~BA166 BA167~BA182 BA183~BA198 BA199~BA214 BA215~BA230 BA231~BA246 BA247~BA262 Block size 8Kwords x 8 64Kwords x 15 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 64Kwords x 16 BK0 1024Kwords 23 Bank # Bank size Number of block BK1 BK2 BK3 BK4 BK5 BK6 BK7 BK8 BK9 BK10 BK11 BK12 BK13 BK14 BK15 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 www..com 2008-03-19 F-73/73 |
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